Implement sqn-'s CPU Vdd levels sysfs interface

file:a7972a36b43819435884b04882703f69eac3d595 -> file:0de7f20637c508710778cf333724d66bb76f2cbc
--- a/arch/arm/mach-msm/acpuclock-scorpion.c
+++ b/arch/arm/mach-msm/acpuclock-scorpion.c
@@ -522,3 +522,41 @@ void __init msm_acpu_clock_init(struct m
clk_set_rate(drv_state.clk_ebi1, drv_state.current_speed->axiclk_khz * 1000);
#endif
}
+
+#ifdef CONFIG_CPU_FREQ_VDD_LEVELS
+
+ssize_t acpuclk_get_vdd_levels_str(char *buf)
+{
+ int i, len = 0;
+ if (buf)
+ {
+ mutex_lock(&drv_state.lock);
+ for (i = 0; acpu_freq_tbl[i].acpu_khz; i++)
+ {
+ if (freq_table[i].frequency != CPUFREQ_ENTRY_INVALID)
+ len += sprintf(buf + len, "%8u: %4d\n", acpu_freq_tbl[i].acpu_khz, acpu_freq_tbl[i].vdd);
+ }
+ mutex_unlock(&drv_state.lock);
+ }
+ return len;
+}
+
+void acpuclk_set_vdd(unsigned acpu_khz, int vdd)
+{
+ int i;
+ vdd = vdd / 25 * 25; //! regulator only accepts multiples of 25 (mV)
+ mutex_lock(&drv_state.lock);
+ for (i = 0; acpu_freq_tbl[i].acpu_khz; i++)
+ {
+ if (freq_table[i].frequency != CPUFREQ_ENTRY_INVALID)
+ {
+ if (acpu_khz == 0)
+ acpu_freq_tbl[i].vdd = min(max((acpu_freq_tbl[i].vdd + vdd), CONFIG_CPU_FREQ_VDD_LEVELS_MIN), CONFIG_CPU_FREQ_VDD_LEVELS_MAX);
+ else if (acpu_freq_tbl[i].acpu_khz == acpu_khz)
+ acpu_freq_tbl[i].vdd = min(max(vdd, CONFIG_CPU_FREQ_VDD_LEVELS_MIN), CONFIG_CPU_FREQ_VDD_LEVELS_MAX);
+ }
+ }
+ mutex_unlock(&drv_state.lock);
+}
+
+#endif
file:b360d9aed77205c82b2a8a1b180d27dd37d95681 -> file:bb2570f4ca245d8ba1b177f74bca7b74a5de4b2b
--- a/arch/arm/mach-msm/board-bravo.c
+++ b/arch/arm/mach-msm/board-bravo.c
@@ -657,8 +657,8 @@ static struct regulator_init_data tps650
{
.constraints = {
.name = "dcdc1", /* VREG_MSMC2_1V29 */
- .min_uV = 925000,
- .max_uV = 1400000,
+ .min_uV = CONFIG_CPU_FREQ_VDD_LEVELS_MIN * 1000,
+ .max_uV = CONFIG_CPU_FREQ_VDD_LEVELS_MAX * 1000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.consumer_supplies = tps65023_dcdc1_supplies,
file:b5a6b4d70f4dfee2afd2eb36390beba0a5595b34 -> file:b572cae65542443d42cf87777c9ce5f7c5a090d3
--- a/arch/arm/mach-msm/board-incrediblec.c
+++ b/arch/arm/mach-msm/board-incrediblec.c
@@ -716,8 +716,8 @@ static struct regulator_init_data tps650
{
.constraints = {
.name = "dcdc1", /* VREG_MSMC2_1V29 */
- .min_uV = 925000,
- .max_uV = 1400000,
+ .min_uV = CONFIG_CPU_FREQ_VDD_LEVELS_MIN * 1000,
+ .max_uV = CONFIG_CPU_FREQ_VDD_LEVELS_MAX * 1000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.consumer_supplies = tps65023_dcdc1_supplies,
file:2bb9ca49db439dfebbd464e1daee50cf34391ea7 -> file:c447a21de9639593ef9b9808ed69ee3d030c48c7
--- a/arch/arm/mach-msm/board-supersonic.c
+++ b/arch/arm/mach-msm/board-supersonic.c
@@ -772,8 +772,8 @@ static struct regulator_init_data tps650
{
.constraints = {
.name = "dcdc1", /* VREG_MSMC2_1V29 */
- .min_uV = 925000,
- .max_uV = 1400000,
+ .min_uV = CONFIG_CPU_FREQ_VDD_LEVELS_MIN * 1000,
+ .max_uV = CONFIG_CPU_FREQ_VDD_LEVELS_MAX * 1000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.consumer_supplies = tps65023_dcdc1_supplies,
file:ce6ea161ef92d444610dc5a76bed94f5ba7ea517 -> file:67ce37adfcd422b9860500515d953fcf141f42ec
--- a/drivers/cpufreq/Kconfig
+++ b/drivers/cpufreq/Kconfig
@@ -220,4 +220,20 @@ config CPU_FREQ_GOV_CONSERVATIVE
If in doubt, say N.
+config CPU_FREQ_VDD_LEVELS
+ bool "CPU Vdd levels sysfs interface"
+ depends on CPU_FREQ_STAT
+ depends on ARCH_QSD8X50
+ default n
+ help
+ CPU Vdd levels sysfs interface
+
+config CPU_FREQ_VDD_LEVELS_MIN
+ int "Min VDD Level"
+ default 1000
+
+config CPU_FREQ_VDD_LEVELS_MAX
+ int "Max VDD Level"
+ default 1300
+
endif # CPU_FREQ
file:c18e65e572c7c3144440bad43ade9a7d507fc4b0 -> file:82ca016d5bbf4a60775ada004f60df3ee7a23104
--- a/drivers/cpufreq/cpufreq.c
+++ b/drivers/cpufreq/cpufreq.c
@@ -647,6 +647,74 @@ static ssize_t show_scaling_setspeed(str
return policy->governor->show_setspeed(policy, buf);
}
+#ifdef CONFIG_CPU_FREQ_VDD_LEVELS
+
+extern ssize_t acpuclk_get_vdd_levels_str(char *buf);
+static ssize_t show_vdd_levels(struct cpufreq_policy *policy, char *buf)
+{
+ return acpuclk_get_vdd_levels_str(buf);
+}
+
+extern void acpuclk_set_vdd(unsigned acpu_khz, int vdd);
+static ssize_t store_vdd_levels(struct cpufreq_policy *policy, const char *buf, size_t count)
+{
+ int i = 0, j;
+ int pair[2] = { 0, 0 };
+ int sign = 0;
+
+ if (count < 1)
+ return 0;
+
+ if (buf[0] == '-')
+ {
+ sign = -1;
+ i++;
+ }
+ else if (buf[0] == '+')
+ {
+ sign = 1;
+ i++;
+ }
+
+ for (j = 0; i < count; i++)
+ {
+ char c = buf[i];
+ if ((c >= '0') && (c <= '9'))
+ {
+ pair[j] *= 10;
+ pair[j] += (c - '0');
+ }
+ else if ((c == ' ') || (c == '\t'))
+ {
+ if (pair[j] != 0)
+ {
+ j++;
+ if ((sign != 0) || (j > 1))
+ break;
+ }
+ }
+ else
+ break;
+ }
+
+ if (sign != 0)
+ {
+ if (pair[0] > 0)
+ acpuclk_set_vdd(0, sign * pair[0]);
+ }
+ else
+ {
+ if ((pair[0] > 0) && (pair[1] > 0))
+ acpuclk_set_vdd((unsigned)pair[0], pair[1]);
+ else
+ return -EINVAL;
+ }
+
+ return count;
+}
+
+#endif
+
#define define_one_ro(_name) \
static struct freq_attr _name = \
__ATTR(_name, 0444, show_##_name, NULL)
@@ -672,6 +740,9 @@ define_one_rw(scaling_min_freq);
define_one_rw(scaling_max_freq);
define_one_rw(scaling_governor);
define_one_rw(scaling_setspeed);
+#ifdef CONFIG_CPU_FREQ_VDD_LEVELS
+define_one_rw(vdd_levels);
+#endif
static struct attribute *default_attrs[] = {
&cpuinfo_min_freq.attr,
@@ -685,6 +756,9 @@ static struct attribute *default_attrs[]
&scaling_driver.attr,
&scaling_available_governors.attr,
&scaling_setspeed.attr,
+#ifdef CONFIG_CPU_FREQ_VDD_LEVELS
+ &vdd_levels.attr,
+#endif
NULL
};