--- arch/x86/include/asm/processor.h

+++ arch/x86/include/asm/processor.h

@@ -765,29 +765,6 @@ extern unsigned long boot_option_idle_o

extern unsigned long idle_halt;

extern unsigned long idle_nomwait;

-/*

- * on systems with caches, caches must be flashed as the absolute

- * last instruction before going into a suspended halt. Otherwise,

- * dirty data can linger in the cache and become stale on resume,

- * leading to strange errors.

- *

- * perform a variety of operations to guarantee that the compiler

- * will not reorder instructions. wbinvd itself is serializing

- * so the processor will not reorder.

- *

- * Systems without cache can just go into halt.

- */

-static inline void wbinvd_halt(void)

-{

- mb();

- /* check for clflush to determine if wbinvd is legal */

- if (cpu_has_clflush)

- asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");

- else

- while (1)

- halt();

-}

-

extern void enable_sep_cpu(void);

extern int sysenter_setup(void);

@@ -1052,4 +1029,23 @@ unsigned long calc_aperfmperf_ratio(stru

return ratio;

}

+/*

+ * AMD errata checking

+ */

+#ifdef CONFIG_CPU_SUP_AMD

+extern const int amd_erratum_400[];

+extern bool cpu_has_amd_erratum(const int *);

+

+#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }

+#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }

+#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \

+ ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))

+#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)

+#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)

+#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)

+

+#else

+#define cpu_has_amd_erratum(x) (false)

+#endif /* CONFIG_CPU_SUP_AMD */

+

#endif /* _ASM_X86_PROCESSOR_H */