--- drivers/gpu/drm/radeon/radeon_cp.c

+++ drivers/gpu/drm/radeon/radeon_cp.c

@@ -417,8 +417,9 @@ static int radeon_do_wait_for_idle(drm_r

return -EBUSY;

}

-static void radeon_init_pipes(drm_radeon_private_t *dev_priv)

+static void radeon_init_pipes(struct drm_device *dev)

{

+ drm_radeon_private_t *dev_priv = dev->dev_private;

uint32_t gb_tile_config, gb_pipe_sel = 0;

if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {

@@ -436,11 +437,12 @@ static void radeon_init_pipes(drm_radeon

dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;

} else {

/* R3xx */

- if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||

+ if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&

+ dev->pdev->device != 0x4144) ||

((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {

dev_priv->num_gb_pipes = 2;

} else {

- /* R3Vxx */

+ /* RV3xx/R300 AD */

dev_priv->num_gb_pipes = 1;

}

}

@@ -736,7 +738,7 @@ static int radeon_do_engine_reset(struct

/* setup the raster pipes */

if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)

- radeon_init_pipes(dev_priv);

+ radeon_init_pipes(dev);

/* Reset the CP ring */

radeon_do_cp_reset(dev_priv);

@@ -1644,6 +1646,7 @@ static int radeon_do_resume_cp(struct dr

radeon_cp_load_microcode(dev_priv);

radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);

+ dev_priv->have_z_offset = 0;

radeon_do_engine_reset(dev);

radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);