--- arch/arm/mach-msm/acpuclock-scorpion.c
+++ arch/arm/mach-msm/acpuclock-scorpion.c
@@ -73,28 +73,34 @@ struct clkctl_acpu_speed {
#define SRC_PLL1 3 /* 768 MHz */
struct clkctl_acpu_speed acpu_freq_tbl[] = {
- { 19200, CCTL(CLK_TCXO, 1), SRC_RAW, 0, 0, 1050, 14000},
- { 128000, CCTL(CLK_TCXO, 1), SRC_AXI, 0, 0, 1050, 14000 },
- { 245000, CCTL(CLK_MODEM_PLL, 1), SRC_RAW, 0, 0, 1050, 29000 },
+ { 19200, CCTL(CLK_TCXO, 1), SRC_RAW, 0, 0, 925, 14000},
+ { 128000, CCTL(CLK_TCXO, 1), SRC_AXI, 0, 0, 925, 14000 },
+ { 245000, CCTL(CLK_MODEM_PLL, 1), SRC_RAW, 0, 0, 925, 29000 },
/* Work arround for acpu resume hung, GPLL is turn off by arm9 */
/*{ 256000, CCTL(CLK_GLOBAL_PLL, 3), SRC_RAW, 0, 0, 1050, 29000 },*/
- { 384000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0A, 0, 1050, 58000 },
- { 422400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0B, 0, 1050, 117000 },
- { 460800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0C, 0, 1050, 117000 },
- { 499200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0D, 0, 1075, 117000 },
- { 537600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0E, 0, 1100, 117000 },
- { 576000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0F, 0, 1100, 117000 },
- { 614400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x10, 0, 1125, 117000 },
- { 652800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x11, 0, 1150, 117000 },
- { 691200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x12, 0, 1175, 117000 },
- { 729600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x13, 0, 1200, 117000 },
- { 768000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x14, 0, 1200, 128000 },
- { 806400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x15, 0, 1225, 128000 },
- { 844800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x16, 0, 1250, 128000 },
- { 883200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x17, 0, 1275, 128000 },
- { 921600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x18, 0, 1300, 128000 },
- { 960000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x19, 0, 1300, 128000 },
- { 998400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1A, 0, 1300, 128000 },
+ { 384000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0A, 0, 975, 58000 },
+ { 422400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0B, 0, 975, 117000 },
+ { 460800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0C, 0, 1000, 117000 },
+ { 499200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0D, 0, 1025, 117000 },
+ { 537600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0E, 0, 1050, 117000 },
+ { 576000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x0F, 0, 1075, 117000 },
+ { 614400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x10, 0, 1075, 117000 },
+ { 652800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x11, 0, 1100, 117000 },
+ { 691200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x12, 0, 1125, 117000 },
+ { 729600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x13, 0, 1150, 117000 },
+ { 768000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x14, 0, 1175, 128000 },
+ { 806400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x15, 0, 1200, 128000 },
+ { 844800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x16, 0, 1200, 128000 },
+ { 883200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x17, 0, 1225, 128000 },
+ { 921600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x18, 0, 1225, 128000 },
+ { 960000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x19, 0, 1250, 128000 },
+ { 998400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1A, 0, 1250, 128000 },
+ { 1036800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1B, 0, 1300, 128000 },
+ { 1075200, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1C, 0, 1300, 128000 },
+ { 1113600, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1D, 0, 1325, 128000 },
+ { 1152000, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1E, 0, 1350, 128000 },
+ { 1190400, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x1F, 0, 1350, 128000 },
+ { 1228800, CCTL(CLK_TCXO, 1), SRC_SCPLL, 0x20, 0, 1400, 128000 },
{ 0 },
};
@@ -134,7 +140,7 @@ static void __init acpuclk_init_cpufreq_
}
/* Take the fastest speed available at the specified VDD level */
- if (vdd != acpu_freq_tbl[i + 1].vdd)
+// if (vdd != acpu_freq_tbl[i + 1].vdd)
freq_table[i].frequency = acpu_freq_tbl[i].acpu_khz;
}
@@ -407,57 +413,6 @@ static int pll_request(unsigned id, unsi
return msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on);
}
-/* Spare register populated with efuse data on max ACPU freq. */
-#define CT_CSR_PHYS 0xA8700000
-#define TCSR_SPARE2_ADDR (ct_csr_base + 0x60)
-
-void __init acpu_freq_tbl_fixup(void)
-{
- void __iomem *ct_csr_base;
- uint32_t tcsr_spare2;
- unsigned int max_acpu_khz;
- unsigned int i;
-
- ct_csr_base = ioremap(CT_CSR_PHYS, PAGE_SIZE);
- BUG_ON(ct_csr_base == NULL);
-
- tcsr_spare2 = readl(TCSR_SPARE2_ADDR);
-
- /* Check if the register is supported and meaningful. */
- if ((tcsr_spare2 & 0xF000) != 0xA000) {
- pr_info("Efuse data on Max ACPU freq not present.\n");
- goto skip_efuse_fixup;
- }
-
- switch (tcsr_spare2 & 0xF0) {
- case 0x70:
- max_acpu_khz = 768000;
- break;
- case 0x30:
- case 0x00:
- max_acpu_khz = 998400;
- break;
- case 0x10:
- max_acpu_khz = 1267200;
- break;
- default:
- pr_warning("Invalid efuse data (%x) on Max ACPU freq!\n",
- tcsr_spare2);
- goto skip_efuse_fixup;
- }
-
- pr_info("Max ACPU freq from efuse data is %d KHz\n", max_acpu_khz);
-
- for (i = 0; acpu_freq_tbl[i].acpu_khz != 0; i++) {
- if (acpu_freq_tbl[i].acpu_khz > max_acpu_khz) {
- acpu_freq_tbl[i].acpu_khz = 0;
- break;
- }
- }
-skip_efuse_fixup:
- iounmap(ct_csr_base);
-}
-
static void __init acpuclk_init(void)
{
struct clkctl_acpu_speed *speed;
@@ -560,7 +515,6 @@ void __init msm_acpu_clock_init(struct m
if (clkdata->mpll_khz)
acpu_mpll->acpu_khz = clkdata->mpll_khz;
- acpu_freq_tbl_fixup();
acpuclk_init();
acpuclk_init_cpufreq_table();
drv_state.clk_ebi1 = clk_get(NULL,"ebi1_clk");
projects / ziggy471-frankenstein-kernel.git / blobdiff