--- arch/x86/include/asm/msr-index.h

+++ arch/x86/include/asm/msr-index.h

@@ -81,11 +81,15 @@

#define MSR_IA32_MC0_ADDR 0x00000402

#define MSR_IA32_MC0_MISC 0x00000403

+#define MSR_AMD64_MC0_MASK 0xc0010044

+

#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))

#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))

#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))

#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))

+#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))

+

/* These are consecutive and not in the normal 4er MCE bank block */

#define MSR_IA32_MC0_CTL2 0x00000280

#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))

@@ -104,6 +108,9 @@

#define MSR_AMD64_PATCH_LEVEL 0x0000008b

#define MSR_AMD64_NB_CFG 0xc001001f

#define MSR_AMD64_PATCH_LOADER 0xc0010020

+#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140

+#define MSR_AMD64_OSVW_STATUS 0xc0010141

+#define MSR_AMD64_DC_CFG 0xc0011022

#define MSR_AMD64_IBSFETCHCTL 0xc0011030

#define MSR_AMD64_IBSFETCHLINAD 0xc0011031

#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032

@@ -123,6 +130,7 @@

#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2

#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffff

#define FAM10H_MMIO_CONF_BASE_SHIFT 20

+#define MSR_FAM10H_NODE_ID 0xc001100c

/* K8 MSRs */

#define MSR_K8_TOP_MEM1 0xc001001a

@@ -195,8 +203,9 @@

#define MSR_IA32_EBL_CR_POWERON 0x0000002a

#define MSR_IA32_FEATURE_CONTROL 0x0000003a

-#define FEATURE_CONTROL_LOCKED (1<<0)

-#define FEATURE_CONTROL_VMXON_ENABLED (1<<2)

+#define FEATURE_CONTROL_LOCKED (1<<0)

+#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)

+#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)

#define MSR_IA32_APICBASE 0x0000001b

#define MSR_IA32_APICBASE_BSP (1<<8)