--- arch/arm/mach-msm/idle-v7.S

+++ arch/arm/mach-msm/idle-v7.S

@@ -42,6 +42,18 @@ ENTRY(msm_pm_collapse)

mrc p15, 0, ip, c13, c0, 1 /* context ID */

stmia r0!, {r1-r9, ip}

+#ifdef CONFIG_MSM_CPU_AVS

+ mrc p15, 7, r1, c15, c1, 7 /* AVSCSR is the Adaptive Voltage Scaling

+ * Control and Status Register */

+ mrc p15, 7, r2, c15, c0, 6 /* AVSDSCR is the Adaptive Voltage

+ * Scaling Delay Synthesizer Control

+ * Register */

+ mrc p15, 7, r3, c15, c1, 0 /* TSCSR is the Temperature Status and

+ * Control Register

+ */

+ stmia r0!, {r1-r3}

+#endif

+

#ifdef CONFIG_VFP

VFPFSTMIA r0, r1 /* Save VFP working registers */

fmrx r1, fpexc

@@ -108,6 +120,12 @@ ENTRY(msm_pm_collapse_exit)

adr r3, msm_pm_collapse_exit

add r1, r1, r3

sub r1, r1, r2

+#ifdef CONFIG_MSM_CPU_AVS

+ ldmdb r1!, {r2-r4}

+ mcr p15, 7, r4, c15, c1, 0 /* TSCSR */

+ mcr p15, 7, r3, c15, c0, 6 /* AVSDSCR */

+ mcr p15, 7, r2, c15, c1, 7 /* AVSCSR */

+#endif

#ifdef CONFIG_VFP

mrc p15, 0, r2, c1, c0, 2 /* Read CP Access Control Register */

orr r2, r2, #0x00F00000 /* Enable full access for p10,11 */

@@ -191,6 +209,9 @@ msm_pm_pa_to_va:

saved_state:

.space 4 * 11 /* r4-14 */

.space 4 * 10 /* cp15 */

+#ifdef CONFIG_MSM_CPU_AVS

+ .space 4 * 3 /* AVS control registers */

+#endif

#ifdef CONFIG_VFP

.space 8 * 32 /* VFP working registers */

.space 4 * 2 /* VFP state registers */