--- include/linux/ssb/ssb_driver_chipcommon.h

+++ include/linux/ssb/ssb_driver_chipcommon.h

@@ -46,7 +46,6 @@

#define SSB_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */

#define SSB_CHIPCO_CAP_PCTL 0x00040000 /* Power Control */

#define SSB_CHIPCO_CAP_OTPS 0x00380000 /* OTP size */

-#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */

#define SSB_CHIPCO_CAP_OTPS_SHIFT 19

#define SSB_CHIPCO_CAP_OTPS_BASE 5

#define SSB_CHIPCO_CAP_JTAGM 0x00400000 /* JTAG master present */

@@ -54,6 +53,7 @@

#define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */

#define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */

#define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */

+#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */

#define SSB_CHIPCO_CORECTL 0x0008

#define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */

#define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */

@@ -386,6 +386,7 @@

/** Chip specific Chip-Status register contents. */

+#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */

#define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003

#define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */

#define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */

@@ -399,6 +400,18 @@

#define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4

#define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */

+/** Macros to determine SPROM presence based on Chip-Status register. */

+#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \

+ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \

+ SSB_CHIPCO_CHST_4325_OTP_SEL)

+#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \

+ (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)

+#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \

+ (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \

+ SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \

+ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \

+ SSB_CHIPCO_CHST_4325_OTP_SEL))

+

/** Clockcontrol masks and values **/