--- a/arch/arm/mm/cache-v7.S

+++ b/arch/arm/mm/cache-v7.S

@@ -154,34 +154,21 @@ ENTRY(v7_coherent_kern_range)

* - the Icache does not read data from the write buffer

*/

ENTRY(v7_coherent_user_range)

- UNWIND(.fnstart )

dcache_line_size r2, r3

sub r3, r2, #1

bic r0, r0, r3

-1:

- USER( mcr p15, 0, r0, c7, c11, 1 ) @ clean D line to the point of unification

+1:

+ mcr p15, 0, r0, c7, c11, 1

dsb

- USER( mcr p15, 0, r0, c7, c5, 1 ) @ invalidate I line

+ mcr p15, 0, r0, c7, c5, 1

add r0, r0, r2

-2:

cmp r0, r1

blo 1b

mov r0, #0

- mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB

+ mcr p15, 0, r0, c7, c5, 6

dsb

isb

mov pc, lr

-

-/*

- * Fault handling for the cache operation above. If the virtual address in r0

- * isn't mapped, just try the next page.

- */

-9001:

- mov r0, r0, lsr #12

- mov r0, r0, lsl #12

- add r0, r0, #4096

- b 2b

- UNWIND(.fnend )

ENDPROC(v7_coherent_kern_range)

ENDPROC(v7_coherent_user_range)