--- arch/arm/Kconfig

+++ arch/arm/Kconfig

@@ -18,9 +18,6 @@ config ARM

select HAVE_KRETPROBES if (HAVE_KPROBES)

select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)

select HAVE_GENERIC_DMA_COHERENT

- select HAVE_KERNEL_GZIP

- select HAVE_KERNEL_LZO

- select HAVE_KERNEL_LZMA

help

The ARM series is a line of low-power-consumption RISC chip designs

licensed by ARM Ltd and targeted at embedded applications and

@@ -118,9 +115,10 @@ config GENERIC_LOCKBREAK

config RWSEM_GENERIC_SPINLOCK

bool

+ default y

config RWSEM_XCHGADD_ALGORITHM

- def_bool y

+ bool

config ARCH_HAS_ILOG2_U32

bool

@@ -892,18 +890,6 @@ config ARM_ERRATA_460075

ACTLR register. Note that setting specific bits in the ACTLR register

may not be available in non-secure mode.

-config ARM_ERRATA_720789

- bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"

- depends on CPU_V7 && SMP

- help

- This option enables the workaround for the 720789 Cortex-A9 (prior to

- r2p0) erratum. A faulty ASID can be sent to the other CPUs for the

- broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.

- As a consequence of this erratum, some TLB entries which should be

- invalidated are not, resulting in an incoherency in the system page

- tables. The workaround changes the TLB flushing routines to invalidate

- entries regardless of the ASID.

-

endmenu

source "arch/arm/common/Kconfig"