From: Ziggy Date: Tue, 4 Sep 2012 15:45:41 +0000 (-0400) Subject: Initial OC/UV X-Git-Url: https://ziggy471.com/git/gitweb.cgi?p=ziggy471-vigor-ics-kernel.git;a=commitdiff;h=57bad04c52e2342c41fd2123055b227a9ddb2bab Initial OC/UV --- --- a/arch/arm/mach-msm/acpuclock-8x60.c +++ b/arch/arm/mach-msm/acpuclock-8x60.c @@ -43,15 +43,16 @@ * The PLL hardware is capable of 384MHz to 1536MHz. The L_VALs * used for calibration should respect these limits. */ #define L_VAL_SCPLL_CAL_MIN 0x08 /* = 432 MHz with 27MHz source */ -#define L_VAL_SCPLL_CAL_MAX 0x1C /* = 1512 MHz with 27MHz source */ +#define L_VAL_SCPLL_CAL_MAX 0x22 /* = 1836 MHz with 27MHz source */ -#define MAX_VDD_SC 1250000 /* uV */ -#define MAX_VDD_MEM 1250000 /* uV */ -#define MAX_VDD_DIG 1200000 /* uV */ -#define MAX_AXI 310500 /* KHz */ +#define MAX_VDD_SC 1600000 /* uV */ +#define MAX_VDD_MEM 1600000 /* uV */ +#define MAX_VDD_DIG 1600000 /* uV */ +#define MAX_AXI 310500 /* KHz */ #define SCPLL_LOW_VDD_FMAX 594000 /* KHz */ #define SCPLL_LOW_VDD 1000000 /* uV */ #define SCPLL_NOMINAL_VDD 1100000 /* uV */ +#define MAX_BOOT_KHZ 1512000 /* KHz */ /* SCPLL Modes. */ #define SCPLL_POWER_DOWN 0 @@ -186,19 +187,20 @@ static struct clkctl_l2_speed l2_freq_tb [13] = {1080000, 1, 0x14, 1100000, 1200000, 2}, [14] = {1134000, 1, 0x15, 1100000, 1200000, 2}, [15] = {1188000, 1, 0x16, 1200000, 1200000, 3}, - [16] = {1242000, 1, 0x17, 1200000, 1212500, 3}, - [17] = {1296000, 1, 0x18, 1200000, 1225000, 3}, - [18] = {1350000, 1, 0x19, 1200000, 1225000, 3}, - [19] = {1404000, 1, 0x1A, 1200000, 1250000, 3}, + [16] = {1404000, 1, 0x1A, 1200000, 1250000, 3}, + [17] = {1620000, 1, 0x1E, 1250000, 1350000, 3}, + [18] = {1728000, 1, 0x20, 1350000, 1450000, 3}, + [19] = {1836000, 1, 0x22, 1450000, 1550000, 3}, + [20] = {1944000, 1, 0x24, 1500000, 1600000, 3}, }; #define L2(x) (&l2_freq_tbl_v2[(x)]) /* SCPLL frequencies = 2 * 27 MHz * L_VAL */ -static struct clkctl_acpu_speed acpu_freq_tbl_1188mhz[] = { - { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 812500, 0x03006000}, +static struct clkctl_acpu_speed acpu_freq_tbl_ziggy[] = { + { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 750000, 0x03006000}, /* MAX_AXI row is used to source CPU cores and L2 from the AFAB clock. */ - { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 875000, 0x03006000}, - { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 875000, 0x03006000}, + { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 812500, 0x03006000}, + { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 812500, 0x03006000}, { {1, 1}, 432000, ACPU_SCPLL, 0, 0, 1, 0x08, L2(1), 887500, 0x03006000}, { {1, 1}, 486000, ACPU_SCPLL, 0, 0, 1, 0x09, L2(2), 912500, 0x03006000}, { {1, 1}, 540000, ACPU_SCPLL, 0, 0, 1, 0x0A, L2(3), 925000, 0x03006000}, @@ -214,100 +216,17 @@ static struct clkctl_acpu_speed acpu_fre { {1, 1}, 1080000, ACPU_SCPLL, 0, 0, 1, 0x14, L2(13), 1137500, 0x03006000}, { {1, 1}, 1134000, ACPU_SCPLL, 0, 0, 1, 0x15, L2(14), 1162500, 0x03006000}, { {1, 1}, 1188000, ACPU_SCPLL, 0, 0, 1, 0x16, L2(15), 1187500, 0x03006000}, + { {1, 1}, 1296000, ACPU_SCPLL, 0, 0, 1, 0x18, L2(15), 1187500, 0x03006000}, + { {1, 1}, 1404000, ACPU_SCPLL, 0, 0, 1, 0x1A, L2(16), 1187500, 0x03006000}, + { {1, 1}, 1512000, ACPU_SCPLL, 0, 0, 1, 0x1C, L2(16), 1250000, 0x03006000}, + { {1, 1}, 1620000, ACPU_SCPLL, 0, 0, 1, 0x1E, L2(16), 1250000, 0x03006000}, + { {1, 1}, 1728000, ACPU_SCPLL, 0, 0, 1, 0x20, L2(17), 1350000, 0x03006000}, + { {1, 1}, 1836000, ACPU_SCPLL, 0, 0, 1, 0x22, L2(18), 1450000, 0x03006000}, + { {0, 0}, 1944000, ACPU_SCPLL, 0, 0, 1, 0x24, L2(19), 1550000, 0x03006000}, + { {0, 0}, 2052000, ACPU_SCPLL, 0, 0, 1, 0x26, L2(20), 1600000, 0x03006000}, { {0, 0}, 0 }, }; -/* SCPLL frequencies = 2 * 27 MHz * L_VAL */ -static struct clkctl_acpu_speed acpu_freq_tbl_slow[] = { - { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 800000, 0x03006000}, - /* MAX_AXI row is used to source CPU cores and L2 from the AFAB clock. */ - { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 825000, 0x03006000}, - { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 825000, 0x03006000}, - { {1, 1}, 432000, ACPU_SCPLL, 0, 0, 1, 0x08, L2(1), 850000, 0x03006000}, - { {1, 1}, 486000, ACPU_SCPLL, 0, 0, 1, 0x09, L2(2), 850000, 0x03006000}, - { {1, 1}, 540000, ACPU_SCPLL, 0, 0, 1, 0x0A, L2(3), 875000, 0x03006000}, - { {1, 1}, 594000, ACPU_SCPLL, 0, 0, 1, 0x0B, L2(4), 875000, 0x03006000}, - { {1, 1}, 648000, ACPU_SCPLL, 0, 0, 1, 0x0C, L2(5), 900000, 0x03006000}, - { {1, 1}, 702000, ACPU_SCPLL, 0, 0, 1, 0x0D, L2(6), 900000, 0x03006000}, - { {1, 1}, 756000, ACPU_SCPLL, 0, 0, 1, 0x0E, L2(7), 925000, 0x03006000}, - { {1, 1}, 810000, ACPU_SCPLL, 0, 0, 1, 0x0F, L2(8), 975000, 0x03006000}, - { {1, 1}, 864000, ACPU_SCPLL, 0, 0, 1, 0x10, L2(9), 975000, 0x03006000}, - { {1, 1}, 918000, ACPU_SCPLL, 0, 0, 1, 0x11, L2(10), 1000000, 0x03006000}, - { {1, 1}, 972000, ACPU_SCPLL, 0, 0, 1, 0x12, L2(11), 1025000, 0x03006000}, - { {1, 1}, 1026000, ACPU_SCPLL, 0, 0, 1, 0x13, L2(12), 1025000, 0x03006000}, - { {1, 1}, 1080000, ACPU_SCPLL, 0, 0, 1, 0x14, L2(13), 1050000, 0x03006000}, - { {1, 1}, 1134000, ACPU_SCPLL, 0, 0, 1, 0x15, L2(14), 1075000, 0x03006000}, - { {1, 1}, 1188000, ACPU_SCPLL, 0, 0, 1, 0x16, L2(15), 1100000, 0x03006000}, - { {1, 1}, 1242000, ACPU_SCPLL, 0, 0, 1, 0x17, L2(16), 1125000, 0x03006000}, - { {1, 1}, 1296000, ACPU_SCPLL, 0, 0, 1, 0x18, L2(17), 1150000, 0x03006000}, - { {1, 1}, 1350000, ACPU_SCPLL, 0, 0, 1, 0x19, L2(18), 1150000, 0x03006000}, - { {1, 1}, 1404000, ACPU_SCPLL, 0, 0, 1, 0x1A, L2(19), 1175000, 0x03006000}, - { {1, 1}, 1458000, ACPU_SCPLL, 0, 0, 1, 0x1B, L2(19), 1200000, 0x03006000}, - { {1, 1}, 1512000, ACPU_SCPLL, 0, 0, 1, 0x1C, L2(19), 1225000, 0x03006000}, - { {0, 0}, 0 }, -}; - -/* SCPLL frequencies = 2 * 27 MHz * L_VAL */ -static struct clkctl_acpu_speed acpu_freq_tbl_nom[] = { - { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 800000, 0x03006000}, - /* MAX_AXI row is used to source CPU cores and L2 from the AFAB clock. */ - { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 825000, 0x03006000}, - { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 825000, 0x03006000}, - { {1, 1}, 432000, ACPU_SCPLL, 0, 0, 1, 0x08, L2(1), 850000, 0x03006000}, - { {1, 1}, 486000, ACPU_SCPLL, 0, 0, 1, 0x09, L2(2), 850000, 0x03006000}, - { {1, 1}, 540000, ACPU_SCPLL, 0, 0, 1, 0x0A, L2(3), 875000, 0x03006000}, - { {1, 1}, 594000, ACPU_SCPLL, 0, 0, 1, 0x0B, L2(4), 875000, 0x03006000}, - { {1, 1}, 648000, ACPU_SCPLL, 0, 0, 1, 0x0C, L2(5), 900000, 0x03006000}, - { {1, 1}, 702000, ACPU_SCPLL, 0, 0, 1, 0x0D, L2(6), 900000, 0x03006000}, - { {1, 1}, 756000, ACPU_SCPLL, 0, 0, 1, 0x0E, L2(7), 925000, 0x03006000}, - { {1, 1}, 810000, ACPU_SCPLL, 0, 0, 1, 0x0F, L2(8), 950000, 0x03006000}, - { {1, 1}, 864000, ACPU_SCPLL, 0, 0, 1, 0x10, L2(9), 975000, 0x03006000}, - { {1, 1}, 918000, ACPU_SCPLL, 0, 0, 1, 0x11, L2(10), 975000, 0x03006000}, - { {1, 1}, 972000, ACPU_SCPLL, 0, 0, 1, 0x12, L2(11), 1000000, 0x03006000}, - { {1, 1}, 1026000, ACPU_SCPLL, 0, 0, 1, 0x13, L2(12), 1000000, 0x03006000}, - { {1, 1}, 1080000, ACPU_SCPLL, 0, 0, 1, 0x14, L2(13), 1025000, 0x03006000}, - { {1, 1}, 1134000, ACPU_SCPLL, 0, 0, 1, 0x15, L2(14), 1025000, 0x03006000}, - { {1, 1}, 1188000, ACPU_SCPLL, 0, 0, 1, 0x16, L2(15), 1050000, 0x03006000}, - { {1, 1}, 1242000, ACPU_SCPLL, 0, 0, 1, 0x17, L2(16), 1075000, 0x03006000}, - { {1, 1}, 1296000, ACPU_SCPLL, 0, 0, 1, 0x18, L2(17), 1100000, 0x03006000}, - { {1, 1}, 1350000, ACPU_SCPLL, 0, 0, 1, 0x19, L2(18), 1125000, 0x03006000}, - { {1, 1}, 1404000, ACPU_SCPLL, 0, 0, 1, 0x1A, L2(19), 1150000, 0x03006000}, - { {1, 1}, 1458000, ACPU_SCPLL, 0, 0, 1, 0x1B, L2(19), 1150000, 0x03006000}, - { {1, 1}, 1512000, ACPU_SCPLL, 0, 0, 1, 0x1C, L2(19), 1175000, 0x03006000}, - { {0, 0}, 0 }, -}; - -/* SCPLL frequencies = 2 * 27 MHz * L_VAL */ -static struct clkctl_acpu_speed acpu_freq_tbl_fast[] = { - { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 800000, 0x03006000}, - /* MAX_AXI row is used to source CPU cores and L2 from the AFAB clock. */ - { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 825000, 0x03006000}, - { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 825000, 0x03006000}, - { {1, 1}, 432000, ACPU_SCPLL, 0, 0, 1, 0x08, L2(1), 850000, 0x03006000}, - { {1, 1}, 486000, ACPU_SCPLL, 0, 0, 1, 0x09, L2(2), 850000, 0x03006000}, - { {1, 1}, 540000, ACPU_SCPLL, 0, 0, 1, 0x0A, L2(3), 875000, 0x03006000}, - { {1, 1}, 594000, ACPU_SCPLL, 0, 0, 1, 0x0B, L2(4), 875000, 0x03006000}, - { {1, 1}, 648000, ACPU_SCPLL, 0, 0, 1, 0x0C, L2(5), 900000, 0x03006000}, - { {1, 1}, 702000, ACPU_SCPLL, 0, 0, 1, 0x0D, L2(6), 900000, 0x03006000}, - { {1, 1}, 756000, ACPU_SCPLL, 0, 0, 1, 0x0E, L2(7), 925000, 0x03006000}, - { {1, 1}, 810000, ACPU_SCPLL, 0, 0, 1, 0x0F, L2(8), 925000, 0x03006000}, - { {1, 1}, 864000, ACPU_SCPLL, 0, 0, 1, 0x10, L2(9), 950000, 0x03006000}, - { {1, 1}, 918000, ACPU_SCPLL, 0, 0, 1, 0x11, L2(10), 950000, 0x03006000}, - { {1, 1}, 972000, ACPU_SCPLL, 0, 0, 1, 0x12, L2(11), 950000, 0x03006000}, - { {1, 1}, 1026000, ACPU_SCPLL, 0, 0, 1, 0x13, L2(12), 975000, 0x03006000}, - { {1, 1}, 1080000, ACPU_SCPLL, 0, 0, 1, 0x14, L2(13), 1000000, 0x03006000}, - { {1, 1}, 1134000, ACPU_SCPLL, 0, 0, 1, 0x15, L2(14), 1000000, 0x03006000}, - { {1, 1}, 1188000, ACPU_SCPLL, 0, 0, 1, 0x16, L2(15), 1025000, 0x03006000}, - { {1, 1}, 1242000, ACPU_SCPLL, 0, 0, 1, 0x17, L2(16), 1050000, 0x03006000}, - { {1, 1}, 1296000, ACPU_SCPLL, 0, 0, 1, 0x18, L2(17), 1075000, 0x03006000}, - { {1, 1}, 1350000, ACPU_SCPLL, 0, 0, 1, 0x19, L2(18), 1100000, 0x03006000}, - { {1, 1}, 1404000, ACPU_SCPLL, 0, 0, 1, 0x1A, L2(19), 1100000, 0x03006000}, - { {1, 1}, 1458000, ACPU_SCPLL, 0, 0, 1, 0x1B, L2(19), 1100000, 0x03006000}, - { {1, 1}, 1512000, ACPU_SCPLL, 0, 0, 1, 0x1C, L2(19), 1125000, 0x03006000}, - { {0, 0}, 0 }, -}; - - /* acpu_freq_tbl row to use when reconfiguring SC/L2 PLLs. */ #define CAL_IDX 1 @@ -669,17 +588,6 @@ out: return rc; } -#ifdef CONFIG_PERFLOCK -unsigned int get_max_cpu_freq(void) -{ - struct clkctl_acpu_speed *f; - for (f = acpu_freq_tbl; f->acpuclk_khz != 0; f++) - ; - f--; - return f->acpuclk_khz;; -} -#endif - static void __init scpll_init(int sc_pll) { uint32_t regval; @@ -802,7 +710,7 @@ static void __init bus_init(void) } #ifdef CONFIG_CPU_FREQ_MSM -static struct cpufreq_frequency_table freq_table[NR_CPUS][30]; +static struct cpufreq_frequency_table freq_table[NR_CPUS][25]; static void __init cpufreq_table_init(void) { @@ -870,59 +778,6 @@ static struct notifier_block __cpuinitda .notifier_call = acpuclock_cpu_callback, }; -static unsigned int __init select_freq_plan(void) -{ - uint32_t pte_efuse, speed_bin, pvs, max_khz; - struct clkctl_acpu_speed *f; - - pte_efuse = readl_relaxed(QFPROM_PTE_EFUSE_ADDR); - - speed_bin = pte_efuse & 0xF; - if (speed_bin == 0xF) - speed_bin = (pte_efuse >> 4) & 0xF; - - if (speed_bin == 0x1) { - max_khz = 1512000; - pvs = (pte_efuse >> 10) & 0x7; - if (pvs == 0x7) - pvs = (pte_efuse >> 13) & 0x7; - - switch (pvs) { - case 0x0: - case 0x7: - acpu_freq_tbl = acpu_freq_tbl_slow; - pr_info("ACPU PVS: Slow\n"); - break; - case 0x1: - acpu_freq_tbl = acpu_freq_tbl_nom; - pr_info("ACPU PVS: Nominal\n"); - break; - case 0x3: - acpu_freq_tbl = acpu_freq_tbl_fast; - pr_info("ACPU PVS: Fast\n"); - break; - default: - acpu_freq_tbl = acpu_freq_tbl_slow; - pr_warn("ACPU PVS: Unknown. Defaulting to slow.\n"); - break; - } - } else { - max_khz = 1188000; - acpu_freq_tbl = acpu_freq_tbl_1188mhz; - } - - /* Truncate the table based to max_khz. */ - for (f = acpu_freq_tbl; f->acpuclk_khz != 0; f++) { - if (f->acpuclk_khz > max_khz) { - f->acpuclk_khz = 0; - break; - } - } - f--; - pr_info("Max ACPU freq: %u KHz\n", f->acpuclk_khz); - - return f->acpuclk_khz; -} static struct acpuclk_data acpuclk_8x60_data = { .set_rate = acpuclk_8x60_set_rate, @@ -935,32 +790,20 @@ int processor_name_read_proc(char *page, int count, int *eof, void *data) { char *p = page; - uint32_t pte_efuse, speed_bin; - - pte_efuse = readl_relaxed(QFPROM_PTE_EFUSE_ADDR); - - speed_bin = pte_efuse & 0xF; - if (speed_bin == 0xF) - speed_bin = (pte_efuse >> 4) & 0xF; - - if (speed_bin == 0x1) - p += sprintf(p, "1.5 GHz dualcore"); - else - p += sprintf(p, "1.2 GHz dualcore"); + p += sprintf(p, "471 GHz dualcoreZ"); return p - page; } static int __init acpuclk_8x60_init(struct acpuclk_soc_data *soc_data) { - unsigned int max_cpu_khz; int cpu; mutex_init(&drv_state.lock); spin_lock_init(&drv_state.l2_lock); /* Configure hardware. */ - max_cpu_khz = select_freq_plan(); + acpu_freq_tbl = acpu_freq_tbl_ziggy; unselect_scplls(); scpll_set_refs(); for_each_possible_cpu(cpu) @@ -971,7 +814,7 @@ static int __init acpuclk_8x60_init(stru /* Improve boot time by ramping up CPUs immediately. */ for_each_online_cpu(cpu) - acpuclk_8x60_set_rate(cpu, max_cpu_khz, SETRATE_INIT); + acpuclk_8x60_set_rate(cpu, MAX_BOOT_KHZ, SETRATE_INIT); acpuclk_register(&acpuclk_8x60_data); cpufreq_table_init(); --- a/arch/arm/mach-msm/avs.h +++ b/arch/arm/mach-msm/avs.h @@ -14,8 +14,8 @@ #ifndef AVS_H #define AVS_H -#define VOLTAGE_MIN 1000 /* mV */ -#define VOLTAGE_MAX 1250 +#define VOLTAGE_MIN 700 /* mV */ +#define VOLTAGE_MAX 1600 #define VOLTAGE_STEP 25 int __init avs_init(int (*set_vdd)(int), u32 freq_cnt, u32 freq_idx); --- a/arch/arm/mach-msm/board-vigor.c +++ b/arch/arm/mach-msm/board-vigor.c @@ -503,8 +503,8 @@ static struct regulator_init_data saw_s0 .constraints = { .name = "8901_s0", .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .min_uV = 840000, - .max_uV = 1250000, + .min_uV = 700000, + .max_uV = 1600000, }, .consumer_supplies = vreg_consumers_8901_S0, .num_consumer_supplies = ARRAY_SIZE(vreg_consumers_8901_S0), @@ -514,8 +514,8 @@ static struct regulator_init_data saw_s1 .constraints = { .name = "8901_s1", .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .min_uV = 840000, - .max_uV = 1250000, + .min_uV = 700000, + .max_uV = 1600000, }, .consumer_supplies = vreg_consumers_8901_S1, .num_consumer_supplies = ARRAY_SIZE(vreg_consumers_8901_S1), @@ -3802,8 +3802,8 @@ static struct regulator_consumer_supply /* RPM early regulator constraints */ static struct rpm_regulator_init_data rpm_regulator_early_init_data[] = { /* ID a_on pd ss min_uV max_uV init_ip freq */ - RPM_SMPS(PM8058_S0, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 1p92), - RPM_SMPS(PM8058_S1, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 1p92), + RPM_SMPS(PM8058_S0, 0, 1, 1, 500000, 1400000, SMPS_HMIN, 1p92), + RPM_SMPS(PM8058_S1, 0, 1, 1, 500000, 1400000, SMPS_HMIN, 1p92), }; /* RPM regulator constraints */ --- a/arch/arm/mach-msm/cpufreq.c +++ b/arch/arm/mach-msm/cpufreq.c @@ -219,6 +219,10 @@ static int __cpuinit msm_cpufreq_init(st init_completion(&cpu_work->complete); #endif +#ifdef CONFIG_MSM_CPU_FREQ_SET_MIN_MAX + policy->min = CONFIG_MSM_CPU_FREQ_MIN; + policy->max = CONFIG_MSM_CPU_FREQ_MAX; +#endif return 0; } @@ -231,6 +235,8 @@ static int msm_cpufreq_suspend(void) per_cpu(cpufreq_suspend, cpu).device_suspended = 1; mutex_unlock(&per_cpu(cpufreq_suspend, cpu).suspend_mutex); } + if (num_online_cpus() > 1) + cpu_down(1); return NOTIFY_DONE; }