--- 3c93426a46ff5f286d8a9cfc13d392ed897ff86a
+++ 6d8b975282c4178afc32b15ed99e6000bcb6cad3
@@ -45,6 +45,7 @@
 #define L_VAL_SCPLL_CAL_MIN	0x08 /* =  432 MHz with 27MHz source */
 #define L_VAL_SCPLL_CAL_MAX	0x22 /* = 1836 MHz with 27MHz source */
 
+#define MIN_VDD_SC     		 700000 /* uV */
 #define MAX_VDD_SC			1600000 /* uV */
 #define MAX_VDD_MEM			1600000 /* uV */
 #define MAX_VDD_DIG			1600000 /* uV */
@@ -826,3 +827,36 @@ static int __init acpuclk_8x60_init(stru
 struct acpuclk_soc_data acpuclk_8x60_soc_data __initdata = {
 	.init = acpuclk_8x60_init,
 };
+
+#ifdef CONFIG_VDD_USERSPACE
+ssize_t acpuclk_get_vdd_levels_str(char *buf)
+{
+	int i, len = 0;
+	if (buf) {
+		mutex_lock(&drv_state.lock);
+		len += sprintf(buf + len, "Min: %4d\n", MIN_VDD_SC);
+		len += sprintf(buf + len, "Max: %4d\n", MAX_VDD_SC);
+		for (i = 0; acpu_freq_tbl[i].acpuclk_khz; i++) {
+			if (acpu_freq_tbl[i].use_for_scaling[0] || acpu_freq_tbl[i].use_for_scaling[1]) {
+				len += sprintf(buf + len, "%8u: %4d\n", acpu_freq_tbl[i].acpuclk_khz, acpu_freq_tbl[i].vdd_sc);
+			}
+		}
+		mutex_unlock(&drv_state.lock);
+	}
+	return len;
+}
+
+void acpuclk_set_vdd(unsigned int khz, int vdd)
+{
+	int i;
+	vdd = vdd / 25 * 25;	//! regulator only accepts multiples of 25 (mV)
+	mutex_lock(&drv_state.lock);
+	for (i = 0; acpu_freq_tbl[i].acpuclk_khz; i++) {
+		if (khz == 0)
+			acpu_freq_tbl[i].vdd_sc = min(max((unsigned int)(acpu_freq_tbl[i].vdd_sc + vdd), (unsigned int)MIN_VDD_SC), (unsigned int)MAX_VDD_SC);
+		else if (acpu_freq_tbl[i].acpuclk_khz == khz)
+			acpu_freq_tbl[i].vdd_sc = min(max((unsigned int)vdd, (unsigned int)MIN_VDD_SC), (unsigned int)MAX_VDD_SC);
+	}
+	mutex_unlock(&drv_state.lock);
+}
+#endif