From: Ziggy Date: Tue, 4 Sep 2012 12:46:31 +0000 (-0400) Subject: Initial OC/UV X-Git-Url: https://ziggy471.com/git/gitweb.cgi?p=ziggy471-shooter-ics-kernel.git;a=commitdiff;h=c97ad043182c7b95a9acd7f607286cca195f0f96 Initial OC/UV --- --- a/arch/arm/mach-msm/acpuclock-8x60.c +++ b/arch/arm/mach-msm/acpuclock-8x60.c @@ -55,6 +55,28 @@ } while (0) +#if defined(pr_debug) +#undef pr_debug +#endif +#define pr_debug(x...) do { \ + printk(KERN_DEBUG "[K][ACPU] "x); \ + } while (0) + +#if defined(pr_info) +#undef pr_info +#endif +#define pr_info(x...) do { \ + printk(KERN_INFO "[K][ACPU] "x); \ + } while (0) + +#if defined(pr_err) +#undef pr_err +#endif +#define pr_err(x...) do { \ + printk(KERN_ERR "[K][ACPU] "x); \ + } while (0) + + /* Frequency switch modes. */ #define SHOT_SWITCH 4 #define HOP_SWITCH 5 @@ -65,14 +87,17 @@ * The PLL hardware has a minimum frequency of 384MHz. * Calibration should respect this limit. */ #define L_VAL_SCPLL_CAL_MIN 0x08 /* = 432 MHz with 27MHz source */ +#define L_VAL_SCPLL_CAL_MAX 0x22 /* = 1836 MHz with 27MHz source */ -#define MAX_VDD_SC 1325000 /* uV */ -#define MAX_VDD_MEM 1325000 /* uV */ -#define MAX_VDD_DIG 1200000 /* uV */ -#define MAX_AXI 310500 /* KHz */ +#define MIN_VDD_SC 700000 /* uV */ +#define MAX_VDD_SC 1400000 /* uV */ +#define MAX_VDD_MEM 1400000 /* uV */ +#define MAX_VDD_DIG 1200000 /* uV */ +#define MAX_AXI 310500 /* KHz */ #define SCPLL_LOW_VDD_FMAX 594000 /* KHz */ #define SCPLL_LOW_VDD 1000000 /* uV */ #define SCPLL_NOMINAL_VDD 1100000 /* uV */ +#define MAX_BOOT_KHZ 1512000 /* KHz */ /* SCPLL Modes. */ #define SCPLL_POWER_DOWN 0 @@ -178,6 +203,7 @@ static struct msm_bus_paths bw_level_tbl [1] = BW_MBPS(1336), /* At least 167 MHz on bus. */ [2] = BW_MBPS(2008), /* At least 251 MHz on bus. */ [3] = BW_MBPS(2480), /* At least 310 MHz on bus. */ + [4] = BW_MBPS(3200), }; static struct msm_bus_scale_pdata bus_client_pdata = { @@ -207,19 +233,19 @@ static struct clkctl_l2_speed l2_freq_tb [13] = {1080000, 1, 0x14, 1100000, 1200000, 2}, [14] = {1134000, 1, 0x15, 1100000, 1200000, 2}, [15] = {1188000, 1, 0x16, 1200000, 1200000, 3}, - [16] = {1242000, 1, 0x17, 1200000, 1212500, 3}, - [17] = {1296000, 1, 0x18, 1200000, 1225000, 3}, - [18] = {1350000, 1, 0x19, 1200000, 1225000, 3}, - [19] = {1404000, 1, 0x1A, 1200000, 1250000, 3}, + [16] = {1404000, 1, 0x1A, 1200000, 1250000, 3}, + [17] = {1620000, 1, 0x1E, 1250000, 1350000, 3}, + [18] = {1728000, 1, 0x20, 1350000, 1450000, 3}, + [19] = {1836000, 1, 0x22, 1350000, 1450000, 3}, }; #define L2(x) (&l2_freq_tbl_v2[(x)]) /* SCPLL frequencies = 2 * 27 MHz * L_VAL */ -static struct clkctl_acpu_speed acpu_freq_tbl_1188mhz[] = { - { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 812500, 0x03006000}, +static struct clkctl_acpu_speed acpu_freq_tbl_ziggy[] = { + { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 750000, 0x03006000}, /* MAX_AXI row is used to source CPU cores and L2 from the AFAB clock. */ - { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 875000, 0x03006000}, - { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 875000, 0x03006000}, + { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 812500, 0x03006000}, + { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 812500, 0x03006000}, { {1, 1}, 432000, ACPU_SCPLL, 0, 0, 1, 0x08, L2(1), 887500, 0x03006000}, { {1, 1}, 486000, ACPU_SCPLL, 0, 0, 1, 0x09, L2(2), 912500, 0x03006000}, { {1, 1}, 540000, ACPU_SCPLL, 0, 0, 1, 0x0A, L2(3), 925000, 0x03006000}, @@ -235,175 +261,16 @@ static struct clkctl_acpu_speed acpu_fre { {1, 1}, 1080000, ACPU_SCPLL, 0, 0, 1, 0x14, L2(13), 1137500, 0x03006000}, { {1, 1}, 1134000, ACPU_SCPLL, 0, 0, 1, 0x15, L2(14), 1162500, 0x03006000}, { {1, 1}, 1188000, ACPU_SCPLL, 0, 0, 1, 0x16, L2(15), 1187500, 0x03006000}, + { {1, 1}, 1296000, ACPU_SCPLL, 0, 0, 1, 0x18, L2(15), 1187500, 0x03006000}, + { {1, 1}, 1404000, ACPU_SCPLL, 0, 0, 1, 0x1A, L2(16), 1187500, 0x03006000}, + { {1, 1}, 1512000, ACPU_SCPLL, 0, 0, 1, 0x1C, L2(16), 1250000, 0x03006000}, + { {1, 1}, 1620000, ACPU_SCPLL, 0, 0, 1, 0x1E, L2(17), 1250000, 0x03006000}, + { {1, 1}, 1728000, ACPU_SCPLL, 0, 0, 1, 0x20, L2(18), 1350000, 0x03006000}, + { {1, 1}, 1836000, ACPU_SCPLL, 0, 0, 1, 0x22, L2(18), 1350000, 0x03006000}, + { {1, 1}, 1944000, ACPU_SCPLL, 0, 0, 1, 0x24, L2(19), 1400000, 0x03006000}, { {0, 0}, 0 }, }; -/* SCPLL frequencies = 2 * 27 MHz * L_VAL */ -static struct clkctl_acpu_speed acpu_freq_tbl_slowest[] = { - { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 800000, 0x03006000}, - /* MAX_AXI row is used to source CPU cores and L2 from the AFAB clock. */ - { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 825000, 0x03006000}, - { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 825000, 0x03006000}, - { {1, 1}, 432000, ACPU_SCPLL, 0, 0, 1, 0x08, L2(1), 850000, 0x03006000}, - { {1, 1}, 486000, ACPU_SCPLL, 0, 0, 1, 0x09, L2(2), 850000, 0x03006000}, - { {1, 1}, 540000, ACPU_SCPLL, 0, 0, 1, 0x0A, L2(3), 875000, 0x03006000}, - { {1, 1}, 594000, ACPU_SCPLL, 0, 0, 1, 0x0B, L2(4), 875000, 0x03006000}, - { {1, 1}, 648000, ACPU_SCPLL, 0, 0, 1, 0x0C, L2(5), 900000, 0x03006000}, - { {1, 1}, 702000, ACPU_SCPLL, 0, 0, 1, 0x0D, L2(6), 900000, 0x03006000}, - { {1, 1}, 756000, ACPU_SCPLL, 0, 0, 1, 0x0E, L2(7), 925000, 0x03006000}, - { {1, 1}, 810000, ACPU_SCPLL, 0, 0, 1, 0x0F, L2(8), 975000, 0x03006000}, - { {1, 1}, 864000, ACPU_SCPLL, 0, 0, 1, 0x10, L2(9), 975000, 0x03006000}, - { {1, 1}, 918000, ACPU_SCPLL, 0, 0, 1, 0x11, L2(10), 1000000, 0x03006000}, - { {1, 1}, 972000, ACPU_SCPLL, 0, 0, 1, 0x12, L2(11), 1025000, 0x03006000}, - { {1, 1}, 1026000, ACPU_SCPLL, 0, 0, 1, 0x13, L2(12), 1025000, 0x03006000}, - { {1, 1}, 1080000, ACPU_SCPLL, 0, 0, 1, 0x14, L2(13), 1050000, 0x03006000}, - { {1, 1}, 1134000, ACPU_SCPLL, 0, 0, 1, 0x15, L2(14), 1075000, 0x03006000}, - { {1, 1}, 1188000, ACPU_SCPLL, 0, 0, 1, 0x16, L2(15), 1100000, 0x03006000}, - { {1, 1}, 1242000, ACPU_SCPLL, 0, 0, 1, 0x17, L2(16), 1125000, 0x03006000}, - { {1, 1}, 1296000, ACPU_SCPLL, 0, 0, 1, 0x18, L2(17), 1150000, 0x03006000}, - { {1, 1}, 1350000, ACPU_SCPLL, 0, 0, 1, 0x19, L2(18), 1175000, 0x03006000}, - { {1, 1}, 1404000, ACPU_SCPLL, 0, 0, 1, 0x1A, L2(19), 1200000, 0x03006000}, - { {1, 1}, 1458000, ACPU_SCPLL, 0, 0, 1, 0x1B, L2(19), 1225000, 0x03006000}, - { {1, 1}, 1512000, ACPU_SCPLL, 0, 0, 1, 0x1C, L2(19), 1250000, 0x03006000}, - { {1, 1}, 1566000, ACPU_SCPLL, 0, 0, 1, 0x1D, L2(19), 1275000, 0x03006000}, - { {1, 1}, 1620000, ACPU_SCPLL, 0, 0, 1, 0x1E, L2(19), 1300000, 0x03006000}, - { {1, 1}, 1674000, ACPU_SCPLL, 0, 0, 1, 0x1F, L2(19), 1325000, 0x03006000}, - { {0, 0}, 0 }, -}; - -/* SCPLL frequencies = 2 * 27 MHz * L_VAL */ -static struct clkctl_acpu_speed acpu_freq_tbl_slower[] = { - { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 800000, 0x03006000}, - /* MAX_AXI row is used to source CPU cores and L2 from the AFAB clock. */ - { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 825000, 0x03006000}, - { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 825000, 0x03006000}, - { {1, 1}, 432000, ACPU_SCPLL, 0, 0, 1, 0x08, L2(1), 850000, 0x03006000}, - { {1, 1}, 486000, ACPU_SCPLL, 0, 0, 1, 0x09, L2(2), 850000, 0x03006000}, - { {1, 1}, 540000, ACPU_SCPLL, 0, 0, 1, 0x0A, L2(3), 875000, 0x03006000}, - { {1, 1}, 594000, ACPU_SCPLL, 0, 0, 1, 0x0B, L2(4), 875000, 0x03006000}, - { {1, 1}, 648000, ACPU_SCPLL, 0, 0, 1, 0x0C, L2(5), 900000, 0x03006000}, - { {1, 1}, 702000, ACPU_SCPLL, 0, 0, 1, 0x0D, L2(6), 900000, 0x03006000}, - { {1, 1}, 756000, ACPU_SCPLL, 0, 0, 1, 0x0E, L2(7), 925000, 0x03006000}, - { {1, 1}, 810000, ACPU_SCPLL, 0, 0, 1, 0x0F, L2(8), 975000, 0x03006000}, - { {1, 1}, 864000, ACPU_SCPLL, 0, 0, 1, 0x10, L2(9), 975000, 0x03006000}, - { {1, 1}, 918000, ACPU_SCPLL, 0, 0, 1, 0x11, L2(10), 1000000, 0x03006000}, - { {1, 1}, 972000, ACPU_SCPLL, 0, 0, 1, 0x12, L2(11), 1025000, 0x03006000}, - { {1, 1}, 1026000, ACPU_SCPLL, 0, 0, 1, 0x13, L2(12), 1025000, 0x03006000}, - { {1, 1}, 1080000, ACPU_SCPLL, 0, 0, 1, 0x14, L2(13), 1050000, 0x03006000}, - { {1, 1}, 1134000, ACPU_SCPLL, 0, 0, 1, 0x15, L2(14), 1075000, 0x03006000}, - { {1, 1}, 1188000, ACPU_SCPLL, 0, 0, 1, 0x16, L2(15), 1100000, 0x03006000}, - { {1, 1}, 1242000, ACPU_SCPLL, 0, 0, 1, 0x17, L2(16), 1125000, 0x03006000}, - { {1, 1}, 1296000, ACPU_SCPLL, 0, 0, 1, 0x18, L2(17), 1150000, 0x03006000}, - { {1, 1}, 1350000, ACPU_SCPLL, 0, 0, 1, 0x19, L2(18), 1150000, 0x03006000}, - { {1, 1}, 1404000, ACPU_SCPLL, 0, 0, 1, 0x1A, L2(19), 1175000, 0x03006000}, - { {1, 1}, 1458000, ACPU_SCPLL, 0, 0, 1, 0x1B, L2(19), 1200000, 0x03006000}, - { {1, 1}, 1512000, ACPU_SCPLL, 0, 0, 1, 0x1C, L2(19), 1225000, 0x03006000}, - { {1, 1}, 1566000, ACPU_SCPLL, 0, 0, 1, 0x1D, L2(19), 1250000, 0x03006000}, - { {1, 1}, 1620000, ACPU_SCPLL, 0, 0, 1, 0x1E, L2(19), 1275000, 0x03006000}, - { {1, 1}, 1674000, ACPU_SCPLL, 0, 0, 1, 0x1F, L2(19), 1300000, 0x03006000}, - { {0, 0}, 0 }, -}; - -/* SCPLL frequencies = 2 * 27 MHz * L_VAL */ -static struct clkctl_acpu_speed acpu_freq_tbl_slow[] = { - { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 800000, 0x03006000}, - /* MAX_AXI row is used to source CPU cores and L2 from the AFAB clock. */ - { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 825000, 0x03006000}, - { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 825000, 0x03006000}, - { {1, 1}, 432000, ACPU_SCPLL, 0, 0, 1, 0x08, L2(1), 850000, 0x03006000}, - { {1, 1}, 486000, ACPU_SCPLL, 0, 0, 1, 0x09, L2(2), 850000, 0x03006000}, - { {1, 1}, 540000, ACPU_SCPLL, 0, 0, 1, 0x0A, L2(3), 875000, 0x03006000}, - { {1, 1}, 594000, ACPU_SCPLL, 0, 0, 1, 0x0B, L2(4), 875000, 0x03006000}, - { {1, 1}, 648000, ACPU_SCPLL, 0, 0, 1, 0x0C, L2(5), 900000, 0x03006000}, - { {1, 1}, 702000, ACPU_SCPLL, 0, 0, 1, 0x0D, L2(6), 900000, 0x03006000}, - { {1, 1}, 756000, ACPU_SCPLL, 0, 0, 1, 0x0E, L2(7), 925000, 0x03006000}, - { {1, 1}, 810000, ACPU_SCPLL, 0, 0, 1, 0x0F, L2(8), 975000, 0x03006000}, - { {1, 1}, 864000, ACPU_SCPLL, 0, 0, 1, 0x10, L2(9), 975000, 0x03006000}, - { {1, 1}, 918000, ACPU_SCPLL, 0, 0, 1, 0x11, L2(10), 1000000, 0x03006000}, - { {1, 1}, 972000, ACPU_SCPLL, 0, 0, 1, 0x12, L2(11), 1025000, 0x03006000}, - { {1, 1}, 1026000, ACPU_SCPLL, 0, 0, 1, 0x13, L2(12), 1025000, 0x03006000}, - { {1, 1}, 1080000, ACPU_SCPLL, 0, 0, 1, 0x14, L2(13), 1050000, 0x03006000}, - { {1, 1}, 1134000, ACPU_SCPLL, 0, 0, 1, 0x15, L2(14), 1075000, 0x03006000}, - { {1, 1}, 1188000, ACPU_SCPLL, 0, 0, 1, 0x16, L2(15), 1100000, 0x03006000}, - { {1, 1}, 1242000, ACPU_SCPLL, 0, 0, 1, 0x17, L2(16), 1125000, 0x03006000}, - { {1, 1}, 1296000, ACPU_SCPLL, 0, 0, 1, 0x18, L2(17), 1150000, 0x03006000}, - { {1, 1}, 1350000, ACPU_SCPLL, 0, 0, 1, 0x19, L2(18), 1150000, 0x03006000}, - { {1, 1}, 1404000, ACPU_SCPLL, 0, 0, 1, 0x1A, L2(19), 1175000, 0x03006000}, - { {1, 1}, 1458000, ACPU_SCPLL, 0, 0, 1, 0x1B, L2(19), 1200000, 0x03006000}, - { {1, 1}, 1512000, ACPU_SCPLL, 0, 0, 1, 0x1C, L2(19), 1225000, 0x03006000}, - { {1, 1}, 1566000, ACPU_SCPLL, 0, 0, 1, 0x1D, L2(19), 1225000, 0x03006000}, - { {1, 1}, 1620000, ACPU_SCPLL, 0, 0, 1, 0x1E, L2(19), 1225000, 0x03006000}, - { {1, 1}, 1674000, ACPU_SCPLL, 0, 0, 1, 0x1F, L2(19), 1250000, 0x03006000}, - { {0, 0}, 0 }, -}; - -/* SCPLL frequencies = 2 * 27 MHz * L_VAL */ -static struct clkctl_acpu_speed acpu_freq_tbl_nom[] = { - { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 800000, 0x03006000}, - /* MAX_AXI row is used to source CPU cores and L2 from the AFAB clock. */ - { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 825000, 0x03006000}, - { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 825000, 0x03006000}, - { {1, 1}, 432000, ACPU_SCPLL, 0, 0, 1, 0x08, L2(1), 850000, 0x03006000}, - { {1, 1}, 486000, ACPU_SCPLL, 0, 0, 1, 0x09, L2(2), 850000, 0x03006000}, - { {1, 1}, 540000, ACPU_SCPLL, 0, 0, 1, 0x0A, L2(3), 875000, 0x03006000}, - { {1, 1}, 594000, ACPU_SCPLL, 0, 0, 1, 0x0B, L2(4), 875000, 0x03006000}, - { {1, 1}, 648000, ACPU_SCPLL, 0, 0, 1, 0x0C, L2(5), 900000, 0x03006000}, - { {1, 1}, 702000, ACPU_SCPLL, 0, 0, 1, 0x0D, L2(6), 900000, 0x03006000}, - { {1, 1}, 756000, ACPU_SCPLL, 0, 0, 1, 0x0E, L2(7), 925000, 0x03006000}, - { {1, 1}, 810000, ACPU_SCPLL, 0, 0, 1, 0x0F, L2(8), 950000, 0x03006000}, - { {1, 1}, 864000, ACPU_SCPLL, 0, 0, 1, 0x10, L2(9), 975000, 0x03006000}, - { {1, 1}, 918000, ACPU_SCPLL, 0, 0, 1, 0x11, L2(10), 975000, 0x03006000}, - { {1, 1}, 972000, ACPU_SCPLL, 0, 0, 1, 0x12, L2(11), 1000000, 0x03006000}, - { {1, 1}, 1026000, ACPU_SCPLL, 0, 0, 1, 0x13, L2(12), 1000000, 0x03006000}, - { {1, 1}, 1080000, ACPU_SCPLL, 0, 0, 1, 0x14, L2(13), 1025000, 0x03006000}, - { {1, 1}, 1134000, ACPU_SCPLL, 0, 0, 1, 0x15, L2(14), 1025000, 0x03006000}, - { {1, 1}, 1188000, ACPU_SCPLL, 0, 0, 1, 0x16, L2(15), 1050000, 0x03006000}, - { {1, 1}, 1242000, ACPU_SCPLL, 0, 0, 1, 0x17, L2(16), 1075000, 0x03006000}, - { {1, 1}, 1296000, ACPU_SCPLL, 0, 0, 1, 0x18, L2(17), 1100000, 0x03006000}, - { {1, 1}, 1350000, ACPU_SCPLL, 0, 0, 1, 0x19, L2(18), 1125000, 0x03006000}, - { {1, 1}, 1404000, ACPU_SCPLL, 0, 0, 1, 0x1A, L2(19), 1150000, 0x03006000}, - { {1, 1}, 1458000, ACPU_SCPLL, 0, 0, 1, 0x1B, L2(19), 1150000, 0x03006000}, - { {1, 1}, 1512000, ACPU_SCPLL, 0, 0, 1, 0x1C, L2(19), 1175000, 0x03006000}, - { {1, 1}, 1566000, ACPU_SCPLL, 0, 0, 1, 0x1D, L2(19), 1175000, 0x03006000}, - { {1, 1}, 1620000, ACPU_SCPLL, 0, 0, 1, 0x1E, L2(19), 1200000, 0x03006000}, - { {1, 1}, 1674000, ACPU_SCPLL, 0, 0, 1, 0x1F, L2(19), 1200000, 0x03006000}, - { {0, 0}, 0 }, -}; - -/* SCPLL frequencies = 2 * 27 MHz * L_VAL */ -static struct clkctl_acpu_speed acpu_freq_tbl_fast[] = { - { {1, 1}, 192000, ACPU_PLL_8, 3, 1, 0, 0, L2(1), 800000, 0x03006000}, - /* MAX_AXI row is used to source CPU cores and L2 from the AFAB clock. */ - { {0, 0}, MAX_AXI, ACPU_AFAB, 1, 0, 0, 0, L2(0), 825000, 0x03006000}, - { {1, 1}, 384000, ACPU_PLL_8, 3, 0, 0, 0, L2(1), 825000, 0x03006000}, - { {1, 1}, 432000, ACPU_SCPLL, 0, 0, 1, 0x08, L2(1), 850000, 0x03006000}, - { {1, 1}, 486000, ACPU_SCPLL, 0, 0, 1, 0x09, L2(2), 850000, 0x03006000}, - { {1, 1}, 540000, ACPU_SCPLL, 0, 0, 1, 0x0A, L2(3), 875000, 0x03006000}, - { {1, 1}, 594000, ACPU_SCPLL, 0, 0, 1, 0x0B, L2(4), 875000, 0x03006000}, - { {1, 1}, 648000, ACPU_SCPLL, 0, 0, 1, 0x0C, L2(5), 900000, 0x03006000}, - { {1, 1}, 702000, ACPU_SCPLL, 0, 0, 1, 0x0D, L2(6), 900000, 0x03006000}, - { {1, 1}, 756000, ACPU_SCPLL, 0, 0, 1, 0x0E, L2(7), 925000, 0x03006000}, - { {1, 1}, 810000, ACPU_SCPLL, 0, 0, 1, 0x0F, L2(8), 925000, 0x03006000}, - { {1, 1}, 864000, ACPU_SCPLL, 0, 0, 1, 0x10, L2(9), 950000, 0x03006000}, - { {1, 1}, 918000, ACPU_SCPLL, 0, 0, 1, 0x11, L2(10), 950000, 0x03006000}, - { {1, 1}, 972000, ACPU_SCPLL, 0, 0, 1, 0x12, L2(11), 950000, 0x03006000}, - { {1, 1}, 1026000, ACPU_SCPLL, 0, 0, 1, 0x13, L2(12), 975000, 0x03006000}, - { {1, 1}, 1080000, ACPU_SCPLL, 0, 0, 1, 0x14, L2(13), 1000000, 0x03006000}, - { {1, 1}, 1134000, ACPU_SCPLL, 0, 0, 1, 0x15, L2(14), 1000000, 0x03006000}, - { {1, 1}, 1188000, ACPU_SCPLL, 0, 0, 1, 0x16, L2(15), 1025000, 0x03006000}, - { {1, 1}, 1242000, ACPU_SCPLL, 0, 0, 1, 0x17, L2(16), 1050000, 0x03006000}, - { {1, 1}, 1296000, ACPU_SCPLL, 0, 0, 1, 0x18, L2(17), 1075000, 0x03006000}, - { {1, 1}, 1350000, ACPU_SCPLL, 0, 0, 1, 0x19, L2(18), 1100000, 0x03006000}, - { {1, 1}, 1404000, ACPU_SCPLL, 0, 0, 1, 0x1A, L2(19), 1100000, 0x03006000}, - { {1, 1}, 1458000, ACPU_SCPLL, 0, 0, 1, 0x1B, L2(19), 1100000, 0x03006000}, - { {1, 1}, 1512000, ACPU_SCPLL, 0, 0, 1, 0x1C, L2(19), 1125000, 0x03006000}, - { {1, 1}, 1566000, ACPU_SCPLL, 0, 0, 1, 0x1D, L2(19), 1125000, 0x03006000}, - { {1, 1}, 1620000, ACPU_SCPLL, 0, 0, 1, 0x1E, L2(19), 1125000, 0x03006000}, - { {1, 1}, 1674000, ACPU_SCPLL, 0, 0, 1, 0x1F, L2(19), 1150000, 0x03006000}, - { {0, 0}, 0 }, -}; - - /* acpu_freq_tbl row to use when reconfiguring SC/L2 PLLs. */ #define CAL_IDX 1 @@ -411,7 +278,7 @@ static struct clkctl_acpu_speed *acpu_fr static struct clkctl_l2_speed *l2_freq_tbl = l2_freq_tbl_v2; static unsigned int l2_freq_tbl_size = ARRAY_SIZE(l2_freq_tbl_v2); -static unsigned long acpuclk_8x60_get_rate(int cpu) +unsigned long acpuclk_8x60_get_rate(int cpu) { return drv_state.current_speed[cpu]->acpuclk_khz; } @@ -769,17 +636,6 @@ out: return rc; } -#ifdef CONFIG_PERFLOCK -unsigned int get_max_cpu_freq(void) -{ - struct clkctl_acpu_speed *f; - for (f = acpu_freq_tbl; f->acpuclk_khz != 0; f++) - ; - f--; - return f->acpuclk_khz;; -} -#endif - static void __init scpll_init(int pll, unsigned int max_l_val) { uint32_t regval; @@ -896,7 +752,7 @@ static void __init bus_init(void) } #ifdef CONFIG_CPU_FREQ_MSM -static struct cpufreq_frequency_table freq_table[NR_CPUS][30]; +static struct cpufreq_frequency_table freq_table[NR_CPUS][26]; static void __init cpufreq_table_init(void) { @@ -966,75 +822,12 @@ static struct notifier_block __cpuinitda static __init struct clkctl_acpu_speed *select_freq_plan(void) { - uint32_t pte_efuse, speed_bin, pvs, max_khz; + uint32_t max_khz; struct clkctl_acpu_speed *f; - pte_efuse = readl_relaxed(QFPROM_PTE_EFUSE_ADDR); + max_khz = 1728000; + acpu_freq_tbl = acpu_freq_tbl_ziggy; - speed_bin = pte_efuse & 0xF; - if (speed_bin == 0xF) - speed_bin = (pte_efuse >> 4) & 0xF; - - pvs = (pte_efuse >> 10) & 0x7; - if (pvs == 0x7) - pvs = (pte_efuse >> 13) & 0x7; - - pr_info("pte_efuse=0x%X, speed_bin=0x%X, pvs=0x%X\n", pte_efuse, speed_bin, pvs); - - if (speed_bin == 0x2) { - max_khz = 1674000; - switch (pvs) { - case 0x7: - case 0x5: - acpu_freq_tbl = acpu_freq_tbl_slowest; - pr_info("ACPU PVS: Slowest\n"); - break; - case 0x4: - acpu_freq_tbl = acpu_freq_tbl_slower; - pr_info("ACPU PVS: Slower\n"); - break; - case 0x0: - acpu_freq_tbl = acpu_freq_tbl_slow; - pr_info("ACPU PVS: Slow\n"); - break; - case 0x1: - acpu_freq_tbl = acpu_freq_tbl_nom; - pr_info("ACPU PVS: Nominal\n"); - break; - case 0x3: - acpu_freq_tbl = acpu_freq_tbl_fast; - pr_info("ACPU PVS: Fast\n"); - break; - default: - acpu_freq_tbl = acpu_freq_tbl_slowest; - pr_warn("ACPU PVS: Unknown. Defaulting to slowest.\n"); - break; - } - } else if (speed_bin == 0x1) { - max_khz = 1512000; - switch (pvs) { - case 0x0: - case 0x7: - acpu_freq_tbl = acpu_freq_tbl_slow; - pr_info("ACPU PVS: Slow\n"); - break; - case 0x1: - acpu_freq_tbl = acpu_freq_tbl_nom; - pr_info("ACPU PVS: Nominal\n"); - break; - case 0x3: - acpu_freq_tbl = acpu_freq_tbl_fast; - pr_info("ACPU PVS: Fast\n"); - break; - default: - acpu_freq_tbl = acpu_freq_tbl_slow; - pr_warn("ACPU PVS: Unknown. Defaulting to slow.\n"); - break; - } - } else { - max_khz = 1188000; - acpu_freq_tbl = acpu_freq_tbl_1188mhz; - } /* Truncate the table based to max_khz. */ for (f = acpu_freq_tbl; f->acpuclk_khz != 0; f++) { @@ -1060,21 +853,7 @@ int processor_name_read_proc(char *page, int count, int *eof, void *data) { char *p = page; - uint32_t pte_efuse, speed_bin; - - pte_efuse = readl_relaxed(QFPROM_PTE_EFUSE_ADDR); - - speed_bin = pte_efuse & 0xF; - if (speed_bin == 0xF) - speed_bin = (pte_efuse >> 4) & 0xF; - - if (speed_bin == 0x2) - p += sprintf(p, "1.7 GHz dual core"); - else if (speed_bin == 0x1) - p += sprintf(p, "1.5 GHz dual core"); - else - p += sprintf(p, "1.2 GHz dual core"); - + p += sprintf(p, "471 GHz dualcoreZ"); return p - page; } @@ -1098,7 +877,7 @@ static int __init acpuclk_8x60_init(stru /* Improve boot time by ramping up CPUs immediately. */ for_each_online_cpu(cpu) - acpuclk_8x60_set_rate(cpu, max_freq->acpuclk_khz, SETRATE_INIT); + acpuclk_8x60_set_rate(cpu, MAX_BOOT_KHZ, SETRATE_INIT); acpuclk_register(&acpuclk_8x60_data); cpufreq_table_init(); --- a/arch/arm/mach-msm/avs.h +++ b/arch/arm/mach-msm/avs.h @@ -14,8 +14,8 @@ #ifndef AVS_H #define AVS_H -#define VOLTAGE_MIN 1000 /* mV */ -#define VOLTAGE_MAX 1250 +#define VOLTAGE_MIN 700 /* mV */ +#define VOLTAGE_MAX 1400 #define VOLTAGE_STEP 25 int __init avs_init(int (*set_vdd)(int), u32 freq_cnt, u32 freq_idx); --- a/arch/arm/mach-msm/board-shooter.c +++ b/arch/arm/mach-msm/board-shooter.c @@ -455,8 +455,8 @@ static struct regulator_init_data saw_s0 .constraints = { .name = "8901_s0", .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .min_uV = 840000, - .max_uV = 1250000, + .min_uV = 700000, + .max_uV = 1400000, }, .consumer_supplies = vreg_consumers_8901_S0, .num_consumer_supplies = ARRAY_SIZE(vreg_consumers_8901_S0), @@ -466,8 +466,8 @@ static struct regulator_init_data saw_s1 .constraints = { .name = "8901_s1", .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .min_uV = 840000, - .max_uV = 1250000, + .min_uV = 700000, + .max_uV = 1400000, }, .consumer_supplies = vreg_consumers_8901_S1, .num_consumer_supplies = ARRAY_SIZE(vreg_consumers_8901_S1), @@ -2850,8 +2850,8 @@ static struct regulator_consumer_supply /* RPM early regulator constraints */ static struct rpm_regulator_init_data rpm_regulator_early_init_data[] = { /* ID a_on pd ss min_uV max_uV init_ip freq */ - RPM_SMPS(PM8058_S0, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 1p92), - RPM_SMPS(PM8058_S1, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 1p92), + RPM_SMPS(PM8058_S0, 0, 1, 1, 500000, 1400000, SMPS_HMIN, 1p92), + RPM_SMPS(PM8058_S1, 0, 1, 1, 500000, 1400000, SMPS_HMIN, 1p92), }; /* RPM regulator constraints */