--- aba851f043cc75b7b89e4f36313558e3f13b4142
+++ 529dfbbac14a25d40946323fba591075d41de02b
@@ -89,10 +89,10 @@
 #define L_VAL_SCPLL_CAL_MIN	0x08 /* =  432 MHz with 27MHz source */
 #define L_VAL_SCPLL_CAL_MAX	0x22 /* = 1836 MHz with 27MHz source */
 
-#define MIN_VDD_SC     		 700000 /* uV */
-#define MAX_VDD_SC			1400000 /* uV */
-#define MAX_VDD_MEM			1400000 /* uV */
-#define MAX_VDD_DIG			1200000 /* uV */
+#define MIN_VDD_SC     		CONFIG_CPU_FREQ_MIN_VDD /* uV */
+#define MAX_VDD_SC			CONFIG_CPU_FREQ_MAX_VDD /* uV */
+#define MAX_VDD_MEM			CONFIG_CPU_FREQ_MAX_VDD /* uV */
+#define MAX_VDD_DIG			CONFIG_CPU_FREQ_MAX_VDD /* uV */
 #define MAX_AXI			 	 310500 /* KHz */
 #define SCPLL_LOW_VDD_FMAX	 594000 /* KHz */
 #define SCPLL_LOW_VDD		1000000 /* uV */