--- drivers/net/wireless/bcmdhd/include/bcmdevs.h
+++ drivers/net/wireless/bcmdhd/include/bcmdevs.h
@@ -152,25 +152,25 @@
#define BCM43131_D11N2G_ID 0x43aa
#define BCM4314_D11N2G_ID 0x4364
#define BCM43142_D11N2G_ID 0x4365
-#define BCM43143_D11N2G_ID 0x4366
+#define BCM43143_D11N2G_ID 0x4366
#define BCM4334_D11N_ID 0x4380
#define BCM4334_D11N2G_ID 0x4381
#define BCM4334_D11N5G_ID 0x4382
-#define BCM43342_D11N_ID 0x4383
-#define BCM43342_D11N2G_ID 0x4384
-#define BCM43342_D11N5G_ID 0x4385
-#define BCM43341_D11N_ID 0x4386
-#define BCM43341_D11N2G_ID 0x4387
-#define BCM43341_D11N5G_ID 0x4388
+#define BCM43342_D11N_ID 0x4383
+#define BCM43342_D11N2G_ID 0x4384
+#define BCM43342_D11N5G_ID 0x4385
+#define BCM43341_D11N_ID 0x4386
+#define BCM43341_D11N2G_ID 0x4387
+#define BCM43341_D11N5G_ID 0x4388
#define BCM4360_D11AC_ID 0x43a0
#define BCM4360_D11AC2G_ID 0x43a1
#define BCM4360_D11AC5G_ID 0x43a2
#define BCM4335_D11AC_ID 0x43ae
#define BCM4335_D11AC2G_ID 0x43af
#define BCM4335_D11AC5G_ID 0x43b0
-#define BCM4352_D11AC_ID 0x43b1
-#define BCM4352_D11AC2G_ID 0x43b2
-#define BCM4352_D11AC5G_ID 0x43b3
+#define BCM4352_D11AC_ID 0x43b1
+#define BCM4352_D11AC2G_ID 0x43b2
+#define BCM4352_D11AC5G_ID 0x43b3
#define BCM943228HMB_SSID_VEN1 0x0607
@@ -178,11 +178,11 @@
#define BCM94313HMG_SSID_VEN1 0x0609
#define BCM943142HM_SSID_VEN1 0x0611
-#define BCM43143_D11N2G_ID 0x4366
+#define BCM43143_D11N2G_ID 0x4366
-#define BCM43242_D11N_ID 0x4367
-#define BCM43242_D11N2G_ID 0x4368
-#define BCM43242_D11N5G_ID 0x4369
+#define BCM43242_D11N_ID 0x4367
+#define BCM43242_D11N2G_ID 0x4368
+#define BCM43242_D11N5G_ID 0x4369
#define BCM4350_D11AC_ID 0x43a3
#define BCM4350_D11AC2G_ID 0x43a4
@@ -225,8 +225,8 @@
#define BCM47XX_GIGETH_ID 0x471f
#define BCM4712_MIPS_ID 0x4720
#define BCM4716_DEVICE_ID 0x4722
-#define BCM47XX_USB30H_ID 0x472a
-#define BCM47XX_USB30D_ID 0x472b
+#define BCM47XX_USB30H_ID 0x472a
+#define BCM47XX_USB30D_ID 0x472b
#define BCM47XX_SMBUS_EMU_ID 0x47fe
#define BCM47XX_XOR_EMU_ID 0x47ff
#define EPI41210_DEVICE_ID 0xa0fa
@@ -282,26 +282,26 @@
#define BCM6362_CHIP_ID 0x6362
#define BCM4314_CHIP_ID 0x4314
#define BCM43142_CHIP_ID 43142
-#define BCM43143_CHIP_ID 43143
+#define BCM43143_CHIP_ID 43143
#define BCM4324_CHIP_ID 0x4324
#define BCM43242_CHIP_ID 43242
-#define BCM43243_CHIP_ID 43243
+#define BCM43243_CHIP_ID 43243
#define BCM4334_CHIP_ID 0x4334
-#define BCM4335_CHIP_ID 0x4335
+#define BCM4335_CHIP_ID 0x4335
#define BCM4360_CHIP_ID 0x4360
#define BCM4352_CHIP_ID 0x4352
#define BCM43526_CHIP_ID 0xAA06
-#define BCM43341_CHIP_ID 43341
-#define BCM43342_CHIP_ID 43342
+#define BCM43341_CHIP_ID 43341
+#define BCM43342_CHIP_ID 43342
#define BCM4335_CHIP_ID 0x4335
-#define BCM4350_CHIP_ID 0x4350
+#define BCM4350_CHIP_ID 0x4350
#define BCM4342_CHIP_ID 4342
#define BCM4402_CHIP_ID 0x4402
#define BCM4704_CHIP_ID 0x4704
#define BCM4706_CHIP_ID 0x5300
-#define BCM4707_CHIP_ID 53010
-#define BCM53018_CHIP_ID 53018
+#define BCM4707_CHIP_ID 53010
+#define BCM53018_CHIP_ID 53018
#define BCM4707_CHIP(chipid) (((chipid) == BCM4707_CHIP_ID) || ((chipid) == BCM53018_CHIP_ID))
#define BCM4710_CHIP_ID 0x4710
#define BCM4712_CHIP_ID 0x4712
@@ -364,17 +364,17 @@
#define BCM4314SDIO_FPBGA_PKG_ID (8 | 4)
#define BCM4314DEV_PKG_ID (8 | 6)
-#define BCM4707_PKG_ID 1
-#define BCM4708_PKG_ID 2
-#define BCM4709_PKG_ID 0
+#define BCM4707_PKG_ID 1
+#define BCM4708_PKG_ID 2
+#define BCM4709_PKG_ID 0
#define PCIXX21_FLASHMEDIA0_ID 0x8033
#define PCIXX21_SDIOH0_ID 0x8034
-#define BCM4335_WLCSP_PKG_ID (0x0)
-#define BCM4335_FCBGA_PKG_ID (0x1)
-#define BCM4335_WLBGA_PKG_ID (0x2)
-#define BCM4335_FCBGAD_PKG_ID (0x3)
+#define BCM4335_WLCSP_PKG_ID (0x0)
+#define BCM4335_FCBGA_PKG_ID (0x1)
+#define BCM4335_WLBGA_PKG_ID (0x2)
+#define BCM4335_FCBGAD_PKG_ID (0x3)
#define BCM4335_PKG_MASK (0x3)
@@ -389,7 +389,7 @@
#define BFL_CCKHIPWR 0x00000040
#define BFL_ENETADM 0x00000080
#define BFL_ENETVLAN 0x00000100
-#define BFL_LTECOEX 0x00000200
+#define BFL_LTECOEX 0x00000200
#define BFL_NOPCI 0x00000400
#define BFL_FEM 0x00000800
#define BFL_EXTLNA 0x00001000
@@ -404,7 +404,7 @@
#define BFL_PHASESHIFT 0x00100000
#define BFL_BUCKBOOST 0x00200000
#define BFL_FEM_BT 0x00400000
-#define BFL_RXCHAIN_OFF_BT 0x00400000
+#define BFL_RXCHAIN_OFF_BT 0x00400000
#define BFL_NOCBUCK 0x00800000
#define BFL_CCKFAVOREVM 0x01000000
#define BFL_PALDO 0x02000000
@@ -413,7 +413,7 @@
#define BFL_UCPWRCTL_MININDX 0x08000000
#define BFL_EXTLNA_5GHz 0x10000000
#define BFL_TRSW_1by2 0x20000000
-#define BFL_GAINBOOSTA01 0x20000000
+#define BFL_GAINBOOSTA01 0x20000000
#define BFL_LO_TRSW_R_5GHz 0x40000000
#define BFL_ELNA_GAINDEF 0x80000000
#define BFL_EXTLNA_TX 0x20000000
@@ -446,8 +446,8 @@
#define BFL2_ANAPACTRL_2G 0x00100000
#define BFL2_ANAPACTRL_5G 0x00200000
#define BFL2_ELNACTRL_TRSW_2G 0x00400000
-#define BFL2_BT_SHARE_ANT0 0x00800000
-#define BFL2_BT_SHARE_BM_BIT0 0x00800000
+#define BFL2_BT_SHARE_ANT0 0x00800000
+#define BFL2_BT_SHARE_BM_BIT0 0x00800000
#define BFL2_TEMPSENSE_HIGHER 0x01000000
#define BFL2_BTC3WIREONLY 0x02000000
#define BFL2_PWR_NOMINAL 0x04000000
@@ -455,31 +455,31 @@
#define BFL2_4313_RADIOREG 0x10000000
-#define BFL2_DYNAMIC_VMID 0x10000000
+#define BFL2_DYNAMIC_VMID 0x10000000
#define BFL2_SDR_EN 0x20000000
-#define BFL2_DYNAMIC_VMID 0x10000000
-#define BFL2_BT_SHARE_BM_BIT1 0x40000000
+#define BFL2_DYNAMIC_VMID 0x10000000
+#define BFL2_BT_SHARE_BM_BIT1 0x40000000
-#define BFL_SROM11_BTCOEX 0x00000001
-#define BFL_SROM11_WLAN_BT_SH_XTL 0x00000002
-#define BFL_SROM11_EXTLNA 0x00001000
-#define BFL_SROM11_EXTLNA_5GHz 0x10000000
-#define BFL_SROM11_GAINBOOSTA01 0x20000000
-#define BFL2_SROM11_APLL_WAR 0x00000002
-#define BFL2_SROM11_ANAPACTRL_2G 0x00100000
-#define BFL2_SROM11_ANAPACTRL_5G 0x00200000
-
-
-#define BFL3_FEMCTRL_SUB 0x00000007
-#define BFL3_RCAL_WAR 0x00000008
-#define BFL3_TXGAINTBLID 0x00000070
-#define BFL3_TXGAINTBLID_SHIFT 0x4
-#define BFL3_TSSI_DIV_WAR 0x00000080
-#define BFL3_TSSI_DIV_WAR_SHIFT 0x7
-#define BFL3_FEMTBL_FROM_NVRAM 0x00000100
-#define BFL3_FEMTBL_FROM_NVRAM_SHIFT 0x8
+#define BFL_SROM11_BTCOEX 0x00000001
+#define BFL_SROM11_WLAN_BT_SH_XTL 0x00000002
+#define BFL_SROM11_EXTLNA 0x00001000
+#define BFL_SROM11_EXTLNA_5GHz 0x10000000
+#define BFL_SROM11_GAINBOOSTA01 0x20000000
+#define BFL2_SROM11_APLL_WAR 0x00000002
+#define BFL2_SROM11_ANAPACTRL_2G 0x00100000
+#define BFL2_SROM11_ANAPACTRL_5G 0x00200000
+
+
+#define BFL3_FEMCTRL_SUB 0x00000007
+#define BFL3_RCAL_WAR 0x00000008
+#define BFL3_TXGAINTBLID 0x00000070
+#define BFL3_TXGAINTBLID_SHIFT 0x4
+#define BFL3_TSSI_DIV_WAR 0x00000080
+#define BFL3_TSSI_DIV_WAR_SHIFT 0x7
+#define BFL3_FEMTBL_FROM_NVRAM 0x00000100
+#define BFL3_FEMTBL_FROM_NVRAM_SHIFT 0x8
#define BOARD_GPIO_BTC3W_IN 0x850
projects / ziggy471-sgs4-jb.git / blobdiff