--- arch/arm/mach-msm/acpuclock-8064.c
+++ arch/arm/mach-msm/acpuclock-8064.c
@@ -47,7 +47,7 @@ static struct scalable scalable[] __init
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x4501,
- .vreg[VREG_CORE] = { "krait0", 1300000 },
+ .vreg[VREG_CORE] = { "krait0", 1450000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
.vreg[VREG_DIG] = { "krait0_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
@@ -58,7 +58,7 @@ static struct scalable scalable[] __init
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x5501,
- .vreg[VREG_CORE] = { "krait1", 1300000 },
+ .vreg[VREG_CORE] = { "krait1", 1450000 },
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
.vreg[VREG_DIG] = { "krait1_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
@@ -69,7 +69,7 @@ static struct scalable scalable[] __init
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x6501,
- .vreg[VREG_CORE] = { "krait2", 1300000 },
+ .vreg[VREG_CORE] = { "krait2", 1450000 },
.vreg[VREG_MEM] = { "krait2_mem", 1150000 },
.vreg[VREG_DIG] = { "krait2_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait2_hfpll", 1800000 },
@@ -80,7 +80,7 @@ static struct scalable scalable[] __init
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x7501,
- .vreg[VREG_CORE] = { "krait3", 1300000 },
+ .vreg[VREG_CORE] = { "krait3", 1450000 },
.vreg[VREG_MEM] = { "krait3_mem", 1150000 },
.vreg[VREG_DIG] = { "krait3_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait3_hfpll", 1800000 },
@@ -116,22 +116,23 @@ static struct msm_bus_scale_pdata bus_sc
};
static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 384000, PLL_8, 0, 0x00 }, 950000, 1050000, 1 },
- [1] = { { 432000, HFPLL, 2, 0x20 }, 1050000, 1050000, 2 },
- [2] = { { 486000, HFPLL, 2, 0x24 }, 1050000, 1050000, 2 },
- [3] = { { 540000, HFPLL, 2, 0x28 }, 1050000, 1050000, 2 },
- [4] = { { 594000, HFPLL, 1, 0x16 }, 1050000, 1050000, 2 },
- [5] = { { 648000, HFPLL, 1, 0x18 }, 1050000, 1050000, 4 },
- [6] = { { 702000, HFPLL, 1, 0x1A }, 1150000, 1150000, 4 },
- [7] = { { 756000, HFPLL, 1, 0x1C }, 1150000, 1150000, 4 },
- [8] = { { 810000, HFPLL, 1, 0x1E }, 1150000, 1150000, 4 },
- [9] = { { 864000, HFPLL, 1, 0x20 }, 1150000, 1150000, 4 },
- [10] = { { 918000, HFPLL, 1, 0x22 }, 1150000, 1150000, 5 },
- [11] = { { 972000, HFPLL, 1, 0x24 }, 1150000, 1150000, 5 },
- [12] = { { 1026000, HFPLL, 1, 0x26 }, 1150000, 1150000, 5 },
- [13] = { { 1080000, HFPLL, 1, 0x28 }, 1150000, 1150000, 5 },
- [14] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 5 },
- [15] = { { 1188000, HFPLL, 1, 0x2C }, 1150000, 1150000, 5 },
+ [0] = { { 378000, HFPLL, 2, 0x1C }, 950000, 1050000, 1 },
+ [1] = { { 384000, PLL_8, 0, 0x00 }, 950000, 1050000, 1 },
+ [2] = { { 432000, HFPLL, 2, 0x20 }, 1050000, 1050000, 2 },
+ [3] = { { 486000, HFPLL, 2, 0x24 }, 1050000, 1050000, 2 },
+ [4] = { { 540000, HFPLL, 2, 0x28 }, 1050000, 1050000, 2 },
+ [5] = { { 594000, HFPLL, 1, 0x16 }, 1050000, 1050000, 2 },
+ [6] = { { 648000, HFPLL, 1, 0x18 }, 1050000, 1050000, 4 },
+ [7] = { { 702000, HFPLL, 1, 0x1A }, 1050000, 1050000, 4 },
+ [8] = { { 756000, HFPLL, 1, 0x1C }, 1150000, 1150000, 4 },
+ [9] = { { 810000, HFPLL, 1, 0x1E }, 1150000, 1150000, 4 },
+ [10] = { { 864000, HFPLL, 1, 0x20 }, 1150000, 1150000, 4 },
+ [11] = { { 918000, HFPLL, 1, 0x22 }, 1150000, 1150000, 5 },
+ [12] = { { 972000, HFPLL, 1, 0x24 }, 1150000, 1150000, 5 },
+ [13] = { { 1026000, HFPLL, 1, 0x26 }, 1150000, 1150000, 5 },
+ [14] = { { 1080000, HFPLL, 1, 0x28 }, 1150000, 1150000, 5 },
+ [15] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 5 },
+ [16] = { { 1188000, HFPLL, 1, 0x2C }, 1150000, 1150000, 5 },
{ }
};
@@ -477,6 +478,34 @@ static struct acpu_level tbl_PVS6_1700MH
{ 0, { 0 } }
};
+static struct acpu_level tbl_ziggy[] __initdata = {
+ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 850000 },
+ { 1, { 216000, HFPLL, 2, 0x10 }, L2(0), 850000 },
+ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 850000 },
+ { 1, { 324000, HFPLL, 2, 0x18 }, L2(0), 875000 },
+ { 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 875000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 900000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 900000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 912500 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 925000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 950000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 975000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(15), 987500 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(15), 1012500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(15), 1050000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(15), 1075000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(15), 1112500 },
+ { 1, { 1782000, HFPLL, 1, 0x42 }, L2(15), 1162500 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(15), 1212500 },
+ { 1, { 1944000, HFPLL, 1, 0x48 }, L2(15), 1237500 },
+ { 1, { 1998000, HFPLL, 1, 0x4A }, L2(15), 1262500 },
+ { 1, { 2052000, HFPLL, 1, 0x4C }, L2(15), 1287500 },
+ { 1, { 2106000, HFPLL, 1, 0x4E }, L2(15), 1312500 },
+ { 0, { 0 } }
+};
+
static struct acpu_level tbl_PVS0_2000MHz[] __initdata = {
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
@@ -632,6 +661,8 @@ static struct pvs_table pvs_tables[NUM_S
[2][5] = { tbl_PVS5_2000MHz, sizeof(tbl_PVS5_2000MHz), 25000 },
[2][6] = { tbl_PVS6_2000MHz, sizeof(tbl_PVS6_2000MHz), 25000 },
+ [7][1] = { tbl_ziggy, sizeof(tbl_ziggy), 25000 },
+
[14][0] = { tbl_PVS0_1512MHz, sizeof(tbl_PVS0_1512MHz), 0 },
[14][1] = { tbl_PVS1_1512MHz, sizeof(tbl_PVS1_1512MHz), 25000 },
[14][2] = { tbl_PVS2_1512MHz, sizeof(tbl_PVS2_1512MHz), 25000 },
projects / ziggy471-sgs4-jb.git / blobdiff