--- a/arch/arm/mach-msm/clock-8960.c
+++ b/arch/arm/mach-msm/clock-8960.c
@@ -3242,10 +3242,9 @@ static struct clk_freq_tbl clk_tbl_gfx2d
F_GFX2D(128000000, pll8, 1, 3),
F_GFX2D(145455000, pll2, 2, 11),
F_GFX2D(160000000, pll2, 1, 5),
- F_GFX2D(228571000, pll2, 2, 9),
- F_GFX2D(266667000, pll2, 1, 4),
- F_GFX2D(300000000, pll2, 2, 7),
- F_GFX2D(320000000, pll2, 1, 3),
+ F_GFX2D(177778000, pll2, 2, 9),
+ F_GFX2D(200000000, pll2, 1, 4),
+ F_GFX2D(228571000, pll2, 2, 7),
F_END
};
@@ -3287,8 +3286,8 @@ static struct rcg_clk gfx2d0_clk = {
.c = {
.dbg_name = "gfx2d0_clk",
.ops = &clk_ops_rcg_8960,
- VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 266667000,
- HIGH, 320000000),
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(gfx2d0_clk.c),
},
};
@@ -3331,8 +3330,8 @@ static struct rcg_clk gfx2d1_clk = {
.c = {
.dbg_name = "gfx2d1_clk",
.ops = &clk_ops_rcg_8960,
- VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 266667000,
- HIGH, 320000000),
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
+ HIGH, 228571000),
CLK_INIT(gfx2d1_clk.c),
},
};
@@ -3362,11 +3361,7 @@ static struct clk_freq_tbl clk_tbl_gfx3d
F_GFX3D(200000000, pll2, 1, 4),
F_GFX3D(228571000, pll2, 2, 7),
F_GFX3D(266667000, pll2, 1, 3),
- F_GFX3D(300000000, pll3, 1, 4),
F_GFX3D(320000000, pll2, 2, 5),
- F_GFX3D(400000000, pll2, 1, 2),
- F_GFX3D(480000000, pll3, 2, 5),
- F_GFX3D(512000000, pll2, 1, 2),
F_END
};
@@ -3388,45 +3383,39 @@ static struct clk_freq_tbl clk_tbl_gfx3d
F_GFX3D(300000000, pll3, 1, 4),
F_GFX3D(320000000, pll2, 2, 5),
F_GFX3D(400000000, pll2, 1, 2),
- F_GFX3D(480000000, pll3, 2, 5),
- F_GFX3D(512000000, pll2, 1, 2),
F_END
};
static unsigned long fmax_gfx3d_8960_v2[MAX_VDD_LEVELS] __initdata = {
[VDD_DIG_LOW] = 128000000,
- [VDD_DIG_NOMINAL] = 320000000,
- [VDD_DIG_HIGH] = 512000000
+ [VDD_DIG_NOMINAL] = 300000000,
+ [VDD_DIG_HIGH] = 400000000
};
static struct clk_freq_tbl clk_tbl_gfx3d_8064[] = {
- F_GFX3D( 0, gnd, 0, 0),
- F_GFX3D( 27000000, pxo, 0, 0),
- F_GFX3D( 48000000, pll8, 1, 8),
- F_GFX3D( 54857000, pll8, 1, 7),
- F_GFX3D( 64000000, pll8, 1, 6),
- F_GFX3D( 76800000, pll8, 1, 5),
- F_GFX3D( 96000000, pll8, 1, 4),
- F_GFX3D(128000000, pll8, 1, 3),
- F_GFX3D(145455000, pll2, 2, 11),
- F_GFX3D(160000000, pll2, 1, 5),
- F_GFX3D(177778000, pll2, 2, 9),
- F_GFX3D(200000000, pll2, 1, 4),
- F_GFX3D(228571000, pll2, 2, 7),
- F_GFX3D(266667000, pll2, 1, 3),
- F_GFX3D(300000000, pll3, 1, 4),
- F_GFX3D(320000000, pll2, 2, 5),
- F_GFX3D(400000000, pll2, 1, 2),
- F_GFX3D(480000000, pll3, 2, 5),
- F_GFX3D(512000000, pll2, 1, 2),
-
+ F_GFX3D( 0, gnd, 0, 0),
+ F_GFX3D( 27000000, pxo, 0, 0),
+ F_GFX3D( 48000000, pll8, 1, 8),
+ F_GFX3D( 54857000, pll8, 1, 7),
+ F_GFX3D( 64000000, pll8, 1, 6),
+ F_GFX3D( 76800000, pll8, 1, 5),
+ F_GFX3D( 96000000, pll8, 1, 4),
+ F_GFX3D(128000000, pll8, 1, 3),
+ F_GFX3D(145455000, pll2, 2, 11),
+ F_GFX3D(160000000, pll2, 1, 5),
+ F_GFX3D(177778000, pll2, 2, 9),
+ F_GFX3D(200000000, pll2, 1, 4),
+ F_GFX3D(228571000, pll2, 2, 7),
+ F_GFX3D(266667000, pll2, 1, 3),
+ F_GFX3D(325000000, pll15, 1, 3),
+ F_GFX3D(400000000, pll2, 1, 2),
F_END
};
static unsigned long fmax_gfx3d_8064[MAX_VDD_LEVELS] __initdata = {
[VDD_DIG_LOW] = 128000000,
[VDD_DIG_NOMINAL] = 325000000,
- [VDD_DIG_HIGH] = 512000000
+ [VDD_DIG_HIGH] = 400000000
};
static struct bank_masks bmnd_info_gfx3d = {
@@ -3467,8 +3456,8 @@ static struct rcg_clk gfx3d_clk = {
.c = {
.dbg_name = "gfx3d_clk",
.ops = &clk_ops_rcg_8960,
- VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 320000000,
- HIGH, 512000000),
+ VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 266667000,
+ HIGH, 320000000),
CLK_INIT(gfx3d_clk.c),
.depends = &gmem_axi_clk.c,
},
@@ -4127,7 +4116,6 @@ static struct clk_freq_tbl clk_tbl_vpe[]
F_VPE( 96000000, pll8, 4),
F_VPE(100000000, pll2, 8),
F_VPE(160000000, pll2, 5),
- F_VPE(200000000, pll2, 4),
F_END
};
@@ -4151,7 +4139,7 @@ static struct rcg_clk vpe_clk = {
.c = {
.dbg_name = "vpe_clk",
.ops = &clk_ops_rcg_8960,
- VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 200000000),
+ VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 160000000),
CLK_INIT(vpe_clk.c),
.depends = &vpe_axi_clk.c,
},
--- a/arch/arm/mach-msm/devices-8960.c
+++ b/arch/arm/mach-msm/devices-8960.c
@@ -2613,7 +2613,7 @@ static struct msm_bus_vectors grp3d_low_
.src = MSM_BUS_MASTER_GRAPHICS_3D,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = KGSL_CONVERT_TO_MBPS(2400), //300 MHz GPU
+ .ib = KGSL_CONVERT_TO_MBPS(1000),
},
};
@@ -2622,7 +2622,7 @@ static struct msm_bus_vectors grp3d_nomi
.src = MSM_BUS_MASTER_GRAPHICS_3D,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = KGSL_CONVERT_TO_MBPS(3200), //400 MHz GPU
+ .ib = KGSL_CONVERT_TO_MBPS(2048),
},
};
@@ -2631,7 +2631,7 @@ static struct msm_bus_vectors grp3d_nomi
.src = MSM_BUS_MASTER_GRAPHICS_3D,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = KGSL_CONVERT_TO_MBPS(3968),
+ .ib = KGSL_CONVERT_TO_MBPS(2656),
},
};
@@ -2640,7 +2640,7 @@ static struct msm_bus_vectors grp3d_max_
.src = MSM_BUS_MASTER_GRAPHICS_3D,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = KGSL_CONVERT_TO_MBPS(5290),
+ .ib = KGSL_CONVERT_TO_MBPS(3968),
},
};
@@ -2687,7 +2687,7 @@ static struct msm_bus_vectors grp2d0_nom
.src = MSM_BUS_MASTER_GRAPHICS_2D_CORE0,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = KGSL_CONVERT_TO_MBPS(2400), //300 MHz
+ .ib = KGSL_CONVERT_TO_MBPS(1000),
},
};
@@ -2696,7 +2696,7 @@ static struct msm_bus_vectors grp2d0_max
.src = MSM_BUS_MASTER_GRAPHICS_2D_CORE0,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = KGSL_CONVERT_TO_MBPS(2560), //320MHz GPU = 2400 Mbps
+ .ib = KGSL_CONVERT_TO_MBPS(2048),
},
};
@@ -2735,7 +2735,7 @@ static struct msm_bus_vectors grp2d1_nom
.src = MSM_BUS_MASTER_GRAPHICS_2D_CORE1,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = KGSL_CONVERT_TO_MBPS(2400), //300 MHz GPU
+ .ib = KGSL_CONVERT_TO_MBPS(1000),
},
};
@@ -2744,7 +2744,7 @@ static struct msm_bus_vectors grp2d1_max
.src = MSM_BUS_MASTER_GRAPHICS_2D_CORE1,
.dst = MSM_BUS_SLAVE_EBI_CH0,
.ab = 0,
- .ib = KGSL_CONVERT_TO_MBPS(2560), // 320Mhz = 2400 Mbps
+ .ib = KGSL_CONVERT_TO_MBPS(2048),
},
};
@@ -2788,32 +2788,31 @@ static struct resource kgsl_3d0_resource
static struct kgsl_device_platform_data kgsl_3d0_pdata = {
.pwrlevel = {
{
- .gpu_freq = 512000000,
+ .gpu_freq = 400000000,
.bus_freq = 4,
.io_fraction = 0,
},
{
- .gpu_freq = 480000000,
+ .gpu_freq = 300000000,
.bus_freq = 3,
- .io_fraction = 0,
+ .io_fraction = 33,
},
{
- .gpu_freq = 400000000,
+ .gpu_freq = 200000000,
.bus_freq = 2,
- .io_fraction = 33,
+ .io_fraction = 100,
},
{
- .gpu_freq = 300000000,
+ .gpu_freq = 128000000,
.bus_freq = 1,
.io_fraction = 100,
},
{
- .gpu_freq = 177778000,
+ .gpu_freq = 27000000,
.bus_freq = 0,
},
},
.init_level = 1,
- .max_level = 0,
.num_levels = 5,
.set_grp_async = NULL,
.idle_timeout = HZ/12,
@@ -2854,11 +2853,11 @@ static struct resource kgsl_2d0_resource
static struct kgsl_device_platform_data kgsl_2d0_pdata = {
.pwrlevel = {
{
- .gpu_freq = 320000000,
+ .gpu_freq = 200000000,
.bus_freq = 2,
},
{
- .gpu_freq = 300000000,
+ .gpu_freq = 96000000,
.bus_freq = 1,
},
{
@@ -2867,7 +2866,6 @@ static struct kgsl_device_platform_data
},
},
.init_level = 0,
- .max_level = 0,
.num_levels = 3,
.set_grp_async = NULL,
.idle_timeout = HZ/5,
@@ -2908,11 +2906,11 @@ static struct resource kgsl_2d1_resource
static struct kgsl_device_platform_data kgsl_2d1_pdata = {
.pwrlevel = {
{
- .gpu_freq = 320000000,
+ .gpu_freq = 200000000,
.bus_freq = 2,
},
{
- .gpu_freq = 300000000,
+ .gpu_freq = 96000000,
.bus_freq = 1,
},
{
@@ -2921,7 +2919,6 @@ static struct kgsl_device_platform_data
},
},
.init_level = 0,
- .max_level = 0,
.num_levels = 3,
.set_grp_async = NULL,
.idle_timeout = HZ/5,
--- a/drivers/gpu/msm/kgsl_pwrctrl.c
+++ b/drivers/gpu/msm/kgsl_pwrctrl.c
@@ -64,17 +64,9 @@ void kgsl_pwrctrl_pwrlevel_change(struct
new_level >= pwr->thermal_pwrlevel &&
new_level != pwr->active_pwrlevel) {
struct kgsl_pwrlevel *pwrlevel = &pwr->pwrlevels[new_level];
- int diff = new_level - pwr->active_pwrlevel;
- int d = (diff > 0) ? 1 : -1;
- int level = pwr->active_pwrlevel;
pwr->active_pwrlevel = new_level;
if ((test_bit(KGSL_PWRFLAGS_CLK_ON, &pwr->power_flags)) ||
(device->state == KGSL_STATE_NAP)) {
- while (level != new_level) {
- level += d;
- clk_set_rate(pwr->grp_clks[0],
- pwr->pwrlevels[level].gpu_freq);
- }
/*
* On some platforms, instability is caused on
* changing clock freq when the core is busy.
@@ -502,7 +494,6 @@ int kgsl_pwrctrl_init(struct kgsl_device
}
pwr->num_pwrlevels = pdata->num_levels;
pwr->active_pwrlevel = pdata->init_level;
- pwr->thermal_pwrlevel = pdata->max_level;
for (i = 0; i < pdata->num_levels; i++) {
pwr->pwrlevels[i].gpu_freq =
(pdata->pwrlevel[i].gpu_freq > 0) ?
--- a/include/linux/msm_kgsl.h
+++ b/include/linux/msm_kgsl.h
@@ -154,7 +154,6 @@ struct kgsl_version {
struct kgsl_device_platform_data {
struct kgsl_pwrlevel pwrlevel[KGSL_MAX_PWRLEVELS];
int init_level;
- int max_level;
int num_levels;
int (*set_grp_async)(void);
unsigned int idle_timeout;
projects / ziggy471-sgs3-jb.git / commitdiff