--- 6ed42fda508447a2ff53e1e1c8f4809ea3c870d5
+++ f8dac2ffeb087f18c40725a629645899b7ba3654
@@ -24,9 +24,9 @@
 #include "acpuclock.h"
 #include <linux/ratelimit.h>
 
-#ifdef CONFIG_SEC_L1_DCACHE_PANIC_CHK
-#include <mach/sec_debug.h>
-#endif
+//#ifdef CONFIG_SEC_L1_DCACHE_PANIC_CHK
+//#include <mach/sec_debug.h>
+//#endif
 
 #define CESR_DCTPE		BIT(0)
 #define CESR_DCDPE		BIT(1)
@@ -344,13 +344,13 @@ static irqreturn_t msm_l1_erp_irq(int ir
 	/* Clear the interrupt bits we processed */
 	write_cesr(cesr);
 
-#ifdef CONFIG_SEC_L1_DCACHE_PANIC_CHK
-	if (print_regs)
-		sec_l1_dcache_check_fail();
-#else
+//#ifdef CONFIG_SEC_L1_DCACHE_PANIC_CHK
+//	if (print_regs)
+//		sec_l1_dcache_check_fail();
+//#else
 	if (print_regs)
 		ERP_L1_ERR("L1 cache error detected");
-#endif
+//#endif
 
 	return IRQ_HANDLED;
 }