--- arch/arm/mach-msm/acpuclock-8960.c
+++ arch/arm/mach-msm/acpuclock-8960.c
@@ -10,6 +10,7 @@
* GNU General Public License for more details.
*/
+#define ZVMIN 900000
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/kernel.h>
@@ -36,7 +37,10 @@
#include <mach/rpm-regulator.h>
#include "acpuclock.h"
-#include "pm.h"
+#if defined(CONFIG_SEC_DEBUG_DCVS_LOG) || defined(CONFIG_SEC_L1_DCACHE_PANIC_CHK)
+#include <mach/sec_debug.h>
+#endif
+
/*
* Source IDs.
@@ -68,17 +72,9 @@
#define STBY_KHZ 1
-#define MAX_VDD_SC 1400000 /* uV */
-#define MIN_VDD_SC 900000 /* uV */
-
-#ifdef CONFIG_VDD_USERSPACE
#define HFPLL_NOMINAL_VDD 1050000
-#define HFPLL_LOW_VDD 700000
-#else
-#define HFPLL_NOMINAL_VDD 1050000
-#define HFPLL_LOW_VDD 850000
-#endif
-#define HFPLL_HIGH_VDD 1400000
+#define HFPLL_LOW_VDD 800000
+#define HFPLL_HIGH_VDD 1350000
#define HFPLL_LOW_VDD_PLL_L_MAX 0x28
#define SECCLKAGD BIT(4)
@@ -357,12 +353,11 @@ static struct scalable scalable_8627[] =
},
};
+static struct scalable *scalable;
static struct l2_level *l2_freq_tbl;
static struct acpu_level *acpu_freq_tbl;
static int l2_freq_tbl_size;
uint32_t global_pvs; /* This code is temporary code */
-static struct scalable *scalable;
-#define SCALABLE_TO_CPU(sc) ((sc) - scalable)
/* Instantaneous bandwidth requests in MB/s. */
#define BW_MBPS(_bw) \
@@ -392,10 +387,6 @@ static struct msm_bus_paths bw_level_tbl
[5] = BW_MBPS(3600), /* At least 450 MHz on bus. */
[6] = BW_MBPS(3936), /* At least 492 MHz on bus. */
[7] = BW_MBPS(4264), /* At least 533 MHz on bus. */
- [8] = BW_MBPS(4532), /* At least 566 MHz on bus. */
- [9] = BW_MBPS(4624), /* At least 578 MHz on bus. */
- [10] = BW_MBPS(4800), /* At least 600 MHz on bus. */
- [11] = BW_MBPS(5336), /* At least 667 MHz on bus. */
};
static struct msm_bus_scale_pdata bus_client_pdata = {
@@ -459,6 +450,283 @@ static struct acpu_level acpu_freq_tbl_8
#undef L2
#define L2(x) (&l2_freq_tbl_8960_kraitv2[(x)])
+#if defined(CONFIG_MSM_CPU_MAX_CLK_1DOT2GHZ)
+
+static struct l2_level l2_freq_tbl_8960_kraitv2[] = {
+ [0] = { {STBY_KHZ, QSB, 0, 0, 0x00 }, 1050000, 1050000, 0 },
+ [1] = { { 384000, PLL_8, 0, 2, 0x00 }, 1050000, 1050000, 1 },
+ [2] = { { 432000, HFPLL, 2, 0, 0x20 }, 1050000, 1050000, 2 },
+ [3] = { { 486000, HFPLL, 2, 0, 0x24 }, 1050000, 1050000, 2 },
+ [4] = { { 540000, HFPLL, 2, 0, 0x28 }, 1050000, 1050000, 2 },
+ [5] = { { 594000, HFPLL, 1, 0, 0x16 }, 1050000, 1050000, 2 },
+ [6] = { { 648000, HFPLL, 1, 0, 0x18 }, 1050000, 1050000, 4 },
+ [7] = { { 702000, HFPLL, 1, 0, 0x1A }, 1050000, 1050000, 4 },
+ [8] = { { 756000, HFPLL, 1, 0, 0x1C }, 1150000, 1150000, 4 },
+ [9] = { { 810000, HFPLL, 1, 0, 0x1E }, 1150000, 1150000, 4 },
+ [10] = { { 864000, HFPLL, 1, 0, 0x20 }, 1150000, 1150000, 4 },
+ [11] = { { 918000, HFPLL, 1, 0, 0x22 }, 1150000, 1150000, 6 },
+ [12] = { { 972000, HFPLL, 1, 0, 0x24 }, 1150000, 1150000, 6 },
+ [13] = { { 1026000, HFPLL, 1, 0, 0x26 }, 1150000, 1150000, 6 },
+ [14] = { { 1080000, HFPLL, 1, 0, 0x28 }, 1150000, 1150000, 6 },
+ [15] = { { 1134000, HFPLL, 1, 0, 0x2A }, 1150000, 1150000, 6 },
+ [16] = { { 1188000, HFPLL, 1, 0, 0x2C }, 1150000, 1150000, 6 },
+ [17] = { { 1242000, HFPLL, 1, 0, 0x2E }, 1150000, 1150000, 6 },
+ [18] = { { 1296000, HFPLL, 1, 0, 0x30 }, 1150000, 1150000, 6 },
+ [19] = { { 1350000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 6 },
+};
+
+static struct acpu_level acpu_freq_tbl_8960_kraitv2_slow[] = {
+ { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 950000 },
+ { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 950000 },
+ { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 975000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 975000 },
+ { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 1000000 },
+ { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(7), 1000000 },
+ { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(7), 1025000 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 1025000 },
+ { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(7), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(7), 1075000 },
+ { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(7), 1100000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(7), 1100000 },
+ { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(7), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(7), 1125000 },
+ { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(16), 1175000 },
+ { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(16), 1175000 },
+ { 1, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1200000 },
+#if 0
+ /* This part is commented out only to MSM8960(1.2GHz) model */
+ { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1200000 },
+ { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1225000 },
+ { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1225000 },
+ { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1237500 },
+ { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(16), 1237500 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(16), 1250000 },
+#endif
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_8960_kraitv2_nom[] = {
+ { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 900000 },
+ { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 925000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 925000 },
+ { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 950000 },
+ { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(7), 950000 },
+ { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(7), 975000 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 975000 },
+ { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(7), 1025000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(7), 1025000 },
+ { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(7), 1050000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(7), 1050000 },
+ { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(7), 1075000 },
+ { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(7), 1075000 },
+ { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(16), 1125000 },
+ { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(16), 1125000 },
+ { 1, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1150000 },
+#if 0
+ /* This part is commented out only to MSM8960(1.2GHz) model */
+ { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1150000 },
+ { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1175000 },
+ { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1175000 },
+ { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1187500 },
+ { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(16), 1187500 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(16), 1200000 },
+#endif
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_8960_kraitv2_fast[] = {
+ { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 850000 },
+ { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 850000 },
+ { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 875000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 875000 },
+ { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 900000 },
+ { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(7), 900000 },
+ { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(7), 925000 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 925000 },
+ { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(7), 975000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(7), 975000 },
+ { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(7), 1000000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(7), 1000000 },
+ { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(7), 1025000 },
+ { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(7), 1025000 },
+ { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(16), 1075000 },
+ { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(16), 1075000 },
+ { 1, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1100000 },
+#if 0
+ /* This part is commented out only to MSM8960(1.2GHz) model */
+ { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1100000 },
+ { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1125000 },
+ { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1125000 },
+ { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1137500 },
+ { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(16), 1137500 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(16), 1150000 },
+#endif
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_8960_kraitv2_f3[] = {
+ { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 850000 },
+ { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 850000 },
+ { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 875000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 875000 },
+ { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 900000 },
+ { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(7), 900000 },
+ { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(7), 925000 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 925000 },
+ { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(7), 975000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(7), 975000 },
+ { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(7), 1000000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(7), 1000000 },
+ { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(7), 1012500 },
+ { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(7), 1012500 },
+ { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(16), 1050000 },
+ { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(16), 1050000 },
+ { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1075000 },
+#if 0
+ { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1075000 },
+ { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1100000 },
+ { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1100000 },
+ { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1112500 },
+ { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(16), 1112500 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(16), 1125000 },
+#endif
+ { 0, { 0 } }
+};
+#elif defined(CONFIG_MSM_DCVS_FOR_MSM8260A)
+
+static struct l2_level l2_freq_tbl_8960_kraitv2[] = {
+ [0] = { {STBY_KHZ, QSB, 0, 0, 0x00 }, 1050000, 1050000, 0 },
+ [1] = { { 384000, PLL_8, 0, 2, 0x00 }, 1050000, 1050000, 1 },
+ [2] = { { 432000, HFPLL, 2, 0, 0x20 }, 1050000, 1050000, 2 },
+ [3] = { { 486000, HFPLL, 2, 0, 0x24 }, 1050000, 1050000, 2 },
+ [4] = { { 540000, HFPLL, 2, 0, 0x28 }, 1050000, 1050000, 2 },
+ [5] = { { 594000, HFPLL, 1, 0, 0x16 }, 1050000, 1050000, 2 },
+ [6] = { { 648000, HFPLL, 1, 0, 0x18 }, 1050000, 1050000, 4 },
+ [7] = { { 702000, HFPLL, 1, 0, 0x1A }, 1050000, 1050000, 4 },
+ [8] = { { 756000, HFPLL, 1, 0, 0x1C }, 1150000, 1150000, 4 },
+ [9] = { { 810000, HFPLL, 1, 0, 0x1E }, 1150000, 1150000, 4 },
+ [10] = { { 864000, HFPLL, 1, 0, 0x20 }, 1150000, 1150000, 4 },
+ [11] = { { 918000, HFPLL, 1, 0, 0x22 }, 1150000, 1150000, 6 },
+ [12] = { { 972000, HFPLL, 1, 0, 0x24 }, 1150000, 1150000, 6 },
+ [13] = { { 1026000, HFPLL, 1, 0, 0x26 }, 1150000, 1150000, 6 },
+ [14] = { { 1080000, HFPLL, 1, 0, 0x28 }, 1150000, 1150000, 6 },
+ [15] = { { 1134000, HFPLL, 1, 0, 0x2A }, 1150000, 1150000, 6 },
+ [16] = { { 1188000, HFPLL, 1, 0, 0x2C }, 1150000, 1150000, 6 },
+ [17] = { { 1242000, HFPLL, 1, 0, 0x2E }, 1150000, 1150000, 6 },
+ [18] = { { 1296000, HFPLL, 1, 0, 0x30 }, 1150000, 1150000, 6 },
+ [19] = { { 1350000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 6 },
+};
+
+static struct acpu_level acpu_freq_tbl_8960_kraitv2_slow[] = {
+ { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 950000 },
+ { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 950000 },
+ { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 975000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 975000 },
+ { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 1000000 },
+ { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(7), 1000000 },
+ { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(7), 1025000 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 1025000 },
+ { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(7), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(7), 1075000 },
+ { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(7), 1100000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(7), 1100000 },
+ { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(7), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(7), 1125000 },
+ { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(16), 1175000 },
+ { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(16), 1175000 },
+ { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1200000 },
+ { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1200000 },
+ { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1225000 },
+ { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1225000 },
+ { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1237500 },
+ { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(16), 1237500 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(16), 1250000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_8960_kraitv2_nom[] = {
+ { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 950000 },
+ { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 950000 },
+ { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 975000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 975000 },
+ { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 1000000 },
+ { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(7), 1000000 },
+ { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(7), 1025000 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 1025000 },
+ { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(7), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(7), 1075000 },
+ { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(7), 1100000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(7), 1100000 },
+ { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(7), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(7), 1125000 },
+ { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(16), 1175000 },
+ { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(16), 1175000 },
+ { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1200000 },
+ { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1200000 },
+ { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1225000 },
+ { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1225000 },
+ { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1237500 },
+ { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(16), 1237500 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(16), 1250000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_8960_kraitv2_fast[] = {
+ { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 900000 },
+ { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 925000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 925000 },
+ { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 950000 },
+ { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(7), 950000 },
+ { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(7), 975000 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 975000 },
+ { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(7), 1025000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(7), 1025000 },
+ { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(7), 1050000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(7), 1050000 },
+ { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(7), 1075000 },
+ { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(7), 1075000 },
+ { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(16), 1125000 },
+ { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(16), 1125000 },
+ { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1150000 },
+ { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1150000 },
+ { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1175000 },
+ { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1175000 },
+ { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1187500 },
+ { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(16), 1187500 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(16), 1200000 },
+ { 0, { 0 } }
+};
+
+static struct acpu_level acpu_freq_tbl_8960_kraitv2_f3[] = {
+ { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 850000 },
+ { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 850000 },
+ { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 875000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 875000 },
+ { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 900000 },
+ { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(7), 900000 },
+ { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(7), 925000 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 925000 },
+ { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(7), 975000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(7), 975000 },
+ { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(7), 1000000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(7), 1000000 },
+ { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(7), 1012500 },
+ { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(7), 1012500 },
+ { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(16), 1050000 },
+ { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(16), 1050000 },
+ { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1075000 },
+ { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1075000 },
+ { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1100000 },
+ { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1100000 },
+ { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1112500 },
+ { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(16), 1112500 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(16), 1125000 },
+ { 0, { 0 } }
+};
+#else
+
static struct l2_level l2_freq_tbl_8960_kraitv2[] = {
[0] = { {STBY_KHZ, QSB, 0, 0, 0x00 }, 1050000, 1050000, 0 },
[1] = { { 384000, PLL_8, 0, 2, 0x00 }, 1050000, 1050000, 1 },
@@ -598,6 +866,8 @@ static struct acpu_level acpu_freq_tbl_8
{ 0, { 0 } }
};
+#endif
+
/* TODO: Update vdd_dig and vdd_mem when voltage data is available. */
#undef L2
#define L2(x) (&l2_freq_tbl_8064[(x)])
@@ -1149,6 +1419,10 @@ static int acpuclk_8960_set_rate(int cpu
pr_debug("Switching from ACPU%d rate %u KHz -> %u KHz\n",
cpu, strt_acpu_s->khz, tgt_acpu_s->khz);
+#ifdef CONFIG_SEC_DEBUG_DCVS_LOG
+ sec_debug_dcvs_log(cpu, strt_acpu_s->khz, tgt_acpu_s->khz);
+#endif
+
/* Set the CPU speed. */
set_speed(&scalable[cpu], tgt_acpu_s, reason);
@@ -1291,7 +1565,7 @@ static void __init bus_init(unsigned int
}
#ifdef CONFIG_CPU_FREQ_MSM
-static struct cpufreq_frequency_table freq_table[NR_CPUS][FREQ_TABLE_SIZE];
+static struct cpufreq_frequency_table freq_table[NR_CPUS][34];
static void __init cpufreq_table_init(void)
{
@@ -1392,8 +1666,8 @@ static const int krait_needs_vmin(void)
static void kraitv2_apply_vmin(struct acpu_level *tbl)
{
for (; tbl->speed.khz != 0; tbl++)
- if (tbl->vdd_core < MIN_VDD_SC)
- tbl->vdd_core = MIN_VDD_SC;
+ if (tbl->vdd_core < ZVMIN)
+ tbl->vdd_core = ZVMIN;
}
#ifdef CONFIG_SEC_L1_DCACHE_PANIC_CHK
@@ -1493,18 +1767,15 @@ static struct acpu_level * __init select
} else {
BUG();
}
-
if (krait_needs_vmin())
kraitv2_apply_vmin(acpu_freq_tbl);
/* Find the max supported scaling frequency. */
- for (l = acpu_freq_tbl; l->speed.khz != 0; l++)
+ for (l = acpu_freq_tbl; l->speed.khz != 0; l++) {
if (l->use_for_scaling)
- if (l->speed.khz <= MAX_FREQ_LIMIT)
- max_acpu_level = l;
- else
- l->use_for_scaling = 0;
-
+ max_acpu_level = l;
+ if (l->speed.khz > 1458000) break;
+ }
BUG_ON(!max_acpu_level);
pr_info("Max ACPU freq: %u KHz\n", max_acpu_level->speed.khz);
@@ -1550,6 +1821,8 @@ ssize_t acpuclk_get_vdd_levels_str(char
int i, len = 0;
if (buf) {
mutex_lock(&driver_lock);
+ len += sprintf(buf + len, "Min: %4d\n", HFPLL_LOW_VDD);
+ len += sprintf(buf + len, "Max: %4d\n", HFPLL_HIGH_VDD);
for (i = 0; acpu_freq_tbl[i].speed.khz; i++) {
len += sprintf(buf + len, "%8u: %4d\n", acpu_freq_tbl[i].speed.khz, acpu_freq_tbl[i].vdd_core);
}
projects / ziggy471-sgs3-jb.git / blobdiff