L2 CACHE: prepare L2 cache to be sync'd with CPU upto 1.512GHz
/arch/arm/mach-msm/acpuclock-8960.c
blob:3712a158cfe406a72bdb5ed900bede117730a949 -> blob:8871caa741eb11990cd9e4198e126163b73a8543
--- arch/arm/mach-msm/acpuclock-8960.c
+++ arch/arm/mach-msm/acpuclock-8960.c
@@ -10,7 +10,6 @@
* GNU General Public License for more details.
*/
-#define ZVMIN 900000
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/kernel.h>
@@ -41,7 +40,6 @@
#include <mach/sec_debug.h>
#endif
-
/*
* Source IDs.
* These must be negative to not overlap with the source IDs
@@ -74,7 +72,6 @@
#define HFPLL_NOMINAL_VDD 1050000
#define HFPLL_LOW_VDD 800000
-#define HFPLL_HIGH_VDD 1350000
#define HFPLL_LOW_VDD_PLL_L_MAX 0x28
#define SECCLKAGD BIT(4)
@@ -597,27 +594,25 @@ static struct acpu_level acpu_freq_tbl_8
static struct l2_level l2_freq_tbl_8960_kraitv2[] = {
[0] = { {STBY_KHZ, QSB, 0, 0, 0x00 }, 1050000, 1050000, 0 },
- [1] = { { 192000, PLL_8, 0, 2, 0x00 }, 1050000, 1050000, 1 }, //133mhz fsb
- [2] = { { 384000, HFPLL, 2, 0, 0x20 }, 1050000, 1050000, 3 }, //266mhz fsb
- [3] = { { 486000, HFPLL, 2, 0, 0x24 }, 1050000, 1050000, 3 }, //266mhz fsb
- [4] = { { 540000, HFPLL, 2, 0, 0x28 }, 1050000, 1050000, 3 }, //266mhz fsb
- [5] = { { 594000, HFPLL, 1, 0, 0x16 }, 1050000, 1050000, 3 }, //266mhz fsb
- [6] = { { 648000, HFPLL, 1, 0, 0x18 }, 1050000, 1050000, 4 }, //400mhz fsb
- [7] = { { 702000, HFPLL, 1, 0, 0x1A }, 1050000, 1050000, 4 }, //400mhz fsb
- [8] = { { 756000, HFPLL, 1, 0, 0x1C }, 1150000, 1150000, 4 }, //400mhz fsb
- [9] = { { 810000, HFPLL, 1, 0, 0x1E }, 1150000, 1150000, 4 }, //400mhz fsb
- [10] = { { 864000, HFPLL, 1, 0, 0x20 }, 1150000, 1150000, 4 }, //400mhz fsb
- [11] = { { 918000, HFPLL, 1, 0, 0x22 }, 1150000, 1150000, 7 }, //533mhz fsb
- [12] = { { 972000, HFPLL, 1, 0, 0x24 }, 1150000, 1150000, 7 }, //533mhz fsb
- [13] = { { 1026000, HFPLL, 1, 0, 0x26 }, 1150000, 1150000, 7 }, //533mhz fsb
- [14] = { { 1080000, HFPLL, 1, 0, 0x28 }, 1150000, 1150000, 7 }, //533mhz fsb
- [15] = { { 1134000, HFPLL, 1, 0, 0x2A }, 1150000, 1150000, 7 }, //533mhz fsb
- [16] = { { 1188000, HFPLL, 1, 0, 0x2C }, 1150000, 1150000, 7 }, //533mhz fsb
- [17] = { { 1242000, HFPLL, 1, 0, 0x2E }, 1150000, 1150000, 7 }, //533mhz fsb
- [18] = { { 1296000, HFPLL, 1, 0, 0x30 }, 1150000, 1150000, 7 }, //533mhz fsb
- [19] = { { 1350000, HFPLL, 1, 0, 0x31 }, 1150000, 1150000, 7 }, //533mhz fsb
- [20] = { { 1458000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 7 }, //533mhz fsb
- [21] = { { 1512000, HFPLL, 1, 0, 0x33 }, 1150000, 1150000, 7 }, //533mhz fsb
+ [1] = { { 384000, PLL_8, 0, 2, 0x00 }, 1050000, 1050000, 1 },
+ [2] = { { 432000, HFPLL, 2, 0, 0x20 }, 1050000, 1050000, 2 },
+ [3] = { { 486000, HFPLL, 2, 0, 0x24 }, 1050000, 1050000, 2 },
+ [4] = { { 540000, HFPLL, 2, 0, 0x28 }, 1050000, 1050000, 2 },
+ [5] = { { 594000, HFPLL, 1, 0, 0x16 }, 1050000, 1050000, 2 },
+ [6] = { { 648000, HFPLL, 1, 0, 0x18 }, 1050000, 1050000, 4 },
+ [7] = { { 702000, HFPLL, 1, 0, 0x1A }, 1050000, 1050000, 4 },
+ [8] = { { 756000, HFPLL, 1, 0, 0x1C }, 1150000, 1150000, 4 },
+ [9] = { { 810000, HFPLL, 1, 0, 0x1E }, 1150000, 1150000, 4 },
+ [10] = { { 864000, HFPLL, 1, 0, 0x20 }, 1150000, 1150000, 4 },
+ [11] = { { 918000, HFPLL, 1, 0, 0x22 }, 1150000, 1150000, 6 },
+ [12] = { { 972000, HFPLL, 1, 0, 0x24 }, 1150000, 1150000, 6 },
+ [13] = { { 1026000, HFPLL, 1, 0, 0x26 }, 1150000, 1150000, 6 },
+ [14] = { { 1080000, HFPLL, 1, 0, 0x28 }, 1150000, 1150000, 6 },
+ [15] = { { 1134000, HFPLL, 1, 0, 0x2A }, 1150000, 1150000, 6 },
+ [16] = { { 1188000, HFPLL, 1, 0, 0x2C }, 1150000, 1150000, 6 },
+ [17] = { { 1242000, HFPLL, 1, 0, 0x2E }, 1150000, 1150000, 6 },
+ [18] = { { 1296000, HFPLL, 1, 0, 0x30 }, 1150000, 1150000, 6 },
+ [19] = { { 1350000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 6 },
};
static struct acpu_level acpu_freq_tbl_8960_kraitv2_slow[] = {
@@ -1668,8 +1663,8 @@ static const int krait_needs_vmin(void)
static void kraitv2_apply_vmin(struct acpu_level *tbl)
{
for (; tbl->speed.khz != 0; tbl++)
- if (tbl->vdd_core < ZVMIN)
- tbl->vdd_core = ZVMIN;
+ if (tbl->vdd_core < 1150000)
+ tbl->vdd_core = 1150000;
}
#ifdef CONFIG_SEC_L1_DCACHE_PANIC_CHK
@@ -1816,31 +1811,3 @@ struct acpuclk_soc_data acpuclk_8960_soc
struct acpuclk_soc_data acpuclk_8930_soc_data __initdata = {
.init = acpuclk_8960_init,
};
-
-#ifdef CONFIG_VDD_USERSPACE
-ssize_t acpuclk_get_vdd_levels_str(char *buf)
-{
- int i, len = 0;
- if (buf) {
- mutex_lock(&driver_lock);
- for (i = 0; acpu_freq_tbl[i].speed.khz; i++) {
- len += sprintf(buf + len, "%8u: %4d\n", acpu_freq_tbl[i].speed.khz, acpu_freq_tbl[i].vdd_core);
- }
- mutex_unlock(&driver_lock);
- }
- return len;
-}
-
-void acpuclk_set_vdd(unsigned int khz, int vdd)
-{
- int i;
- mutex_lock(&driver_lock);
- for (i = 0; acpu_freq_tbl[i].speed.khz; i++) {
- if (khz == 0)
- acpu_freq_tbl[i].vdd_core = min(max((unsigned int)(acpu_freq_tbl[i].vdd_core + vdd), (unsigned int)HFPLL_LOW_VDD), (unsigned int)HFPLL_HIGH_VDD);
- else if (acpu_freq_tbl[i].speed.khz == khz)
- acpu_freq_tbl[i].vdd_core = min(max((unsigned int)vdd, (unsigned int)HFPLL_LOW_VDD), (unsigned int)HFPLL_HIGH_VDD);
- }
- mutex_unlock(&driver_lock);
-}
-#endif