--- arch/arm/mach-msm/acpuclock-8960.c
+++ arch/arm/mach-msm/acpuclock-8960.c
@@ -10,6 +10,7 @@
* GNU General Public License for more details.
*/
+#define ZVMIN 900000
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/kernel.h>
@@ -40,6 +41,7 @@
#include <mach/sec_debug.h>
#endif
+
/*
* Source IDs.
* These must be negative to not overlap with the source IDs
@@ -71,7 +73,8 @@
#define STBY_KHZ 1
#define HFPLL_NOMINAL_VDD 1050000
-#define HFPLL_LOW_VDD 850000
+#define HFPLL_LOW_VDD 800000
+#define HFPLL_HIGH_VDD 1350000
#define HFPLL_LOW_VDD_PLL_L_MAX 0x28
#define SECCLKAGD BIT(4)
@@ -144,7 +147,7 @@ static struct scalable scalable_8960[] =
.hfpll_base = MSM_HFPLL_BASE + 0x200,
.aux_clk_sel = MSM_ACC0_BASE + 0x014,
.l2cpmr_iaddr = L2CPUCPMR_IADDR,
- .vreg[VREG_CORE] = { "krait0", 1300000 },
+ .vreg[VREG_CORE] = { "krait0", 1350000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000,
RPM_VREG_VOTER1,
RPM_VREG_ID_PM8921_L24 },
@@ -162,7 +165,7 @@ static struct scalable scalable_8960[] =
.hfpll_base = MSM_HFPLL_BASE + 0x300,
.aux_clk_sel = MSM_ACC1_BASE + 0x014,
.l2cpmr_iaddr = L2CPUCPMR_IADDR,
- .vreg[VREG_CORE] = { "krait1", 1300000 },
+ .vreg[VREG_CORE] = { "krait1", 1350000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000,
RPM_VREG_VOTER2,
RPM_VREG_ID_PM8921_L24 },
@@ -383,6 +386,7 @@ static struct msm_bus_paths bw_level_tbl
[4] = BW_MBPS(3200), /* At least 400 MHz on bus. */
[5] = BW_MBPS(3600), /* At least 450 MHz on bus. */
[6] = BW_MBPS(3936), /* At least 492 MHz on bus. */
+ [7] = BW_MBPS(4264), /* At least 533 MHz on bus. */
};
static struct msm_bus_scale_pdata bus_client_pdata = {
@@ -740,10 +744,10 @@ static struct l2_level l2_freq_tbl_8960_
[13] = { { 1026000, HFPLL, 1, 0, 0x26 }, 1150000, 1150000, 6 },
[14] = { { 1080000, HFPLL, 1, 0, 0x28 }, 1150000, 1150000, 6 },
[15] = { { 1134000, HFPLL, 1, 0, 0x2A }, 1150000, 1150000, 6 },
- [16] = { { 1188000, HFPLL, 1, 0, 0x2C }, 1150000, 1150000, 6 },
- [17] = { { 1242000, HFPLL, 1, 0, 0x2E }, 1150000, 1150000, 6 },
- [18] = { { 1296000, HFPLL, 1, 0, 0x30 }, 1150000, 1150000, 6 },
- [19] = { { 1350000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 6 },
+ [16] = { { 1188000, HFPLL, 1, 0, 0x2C }, 1150000, 1150000, 7 },
+ [17] = { { 1242000, HFPLL, 1, 0, 0x2E }, 1150000, 1150000, 7 },
+ [18] = { { 1296000, HFPLL, 1, 0, 0x30 }, 1150000, 1150000, 7 },
+ [19] = { { 1350000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 7 },
};
static struct acpu_level acpu_freq_tbl_8960_kraitv2_slow[] = {
@@ -774,37 +778,41 @@ static struct acpu_level acpu_freq_tbl_8
};
static struct acpu_level acpu_freq_tbl_8960_kraitv2_nom[] = {
- { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 900000 },
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 900000 },
- { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 925000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 925000 },
- { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 950000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(7), 950000 },
- { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(7), 975000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 975000 },
- { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(7), 1025000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(7), 1025000 },
- { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(7), 1050000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(7), 1050000 },
- { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(7), 1075000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(7), 1075000 },
- { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(16), 1125000 },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(16), 1125000 },
- { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1150000 },
- { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1150000 },
- { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1175000 },
- { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1175000 },
- { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1187500 },
- { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(16), 1187500 },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(16), 1200000 },
+ { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 800000 },
+ { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 800000 },
+ { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 825000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 850000 },
+ { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 850000 },
+ { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(7), 850000 },
+ { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(7), 900000 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 900000 },
+ { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(7), 950000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(7), 950000 },
+ { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(7), 975000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(7), 975000 },
+ { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(7), 1025000 },
+ { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(7), 1025000 },
+ { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(16), 1050000 },
+ { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(16), 1050000 },
+ { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1075000 },
+ { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1075000 },
+ { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1125000 },
+ { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1125000 },
+ { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1125000 },
+ { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(16), 1150000 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(18), 1150000 },
+ { 1, { 1674000, HFPLL, 1, 0, 0x3A }, L2(18), 1200000 },
+ { 1, { 1728000, HFPLL, 1, 0, 0x3C }, L2(19), 1200000 },
+ { 1, { 1809000, HFPLL, 1, 0, 0x3E }, L2(19), 1250000 },
+ { 1, { 1900000, HFPLL, 1, 0, 0x40 }, L2(19), 1300000 },
{ 0, { 0 } }
};
static struct acpu_level acpu_freq_tbl_8960_kraitv2_fast[] = {
{ 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 850000 },
{ 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 850000 },
- { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 875000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 875000 },
+ { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 850000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 850000 },
{ 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 900000 },
{ 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(7), 900000 },
{ 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(7), 925000 },
@@ -821,9 +829,13 @@ static struct acpu_level acpu_freq_tbl_8
{ 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1100000 },
{ 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1125000 },
{ 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1125000 },
- { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1137500 },
+ { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1125000 },
{ 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(16), 1137500 },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(16), 1150000 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(18), 1150000 },
+ { 1, { 1674000, HFPLL, 1, 0, 0x3A }, L2(18), 1175000 },
+ { 1, { 1728000, HFPLL, 1, 0, 0x3C }, L2(19), 1200000 },
+ { 1, { 1809000, HFPLL, 1, 0, 0x3E }, L2(19), 1250000 },
+ { 1, { 1998000, HFPLL, 1, 0, 0x42 }, L2(19), 1300000 },
{ 0, { 0 } }
};
@@ -1553,7 +1565,7 @@ static void __init bus_init(unsigned int
}
#ifdef CONFIG_CPU_FREQ_MSM
-static struct cpufreq_frequency_table freq_table[NR_CPUS][30];
+static struct cpufreq_frequency_table freq_table[NR_CPUS][34];
static void __init cpufreq_table_init(void)
{
@@ -1654,8 +1666,8 @@ static const int krait_needs_vmin(void)
static void kraitv2_apply_vmin(struct acpu_level *tbl)
{
for (; tbl->speed.khz != 0; tbl++)
- if (tbl->vdd_core < 1150000)
- tbl->vdd_core = 1150000;
+ if (tbl->vdd_core < ZVMIN)
+ tbl->vdd_core = ZVMIN;
}
#ifdef CONFIG_SEC_L1_DCACHE_PANIC_CHK
@@ -1703,51 +1715,15 @@ static struct acpu_level * __init select
pr_alert("ACPU PVS:[%d],FMAX[%d]\n", pvs, fmax);
switch (pvs) {
- case 0x0:
- case 0x7:
- pr_alert("ACPU PVS: Slow(L%d)\n",
- pvs_leakage);
- v1 = acpu_freq_tbl_8960_kraitv1_slow;
- v2 = acpu_freq_tbl_8960_kraitv2_slow;
- break;
- case 0x1:
- pr_alert("ACPU PVS: Nominal(L%d)\n",
- pvs_leakage);
- v1 = acpu_freq_tbl_8960_kraitv1_nom_fast;
- v2 = acpu_freq_tbl_8960_kraitv2_nom;
- break;
- case 0x3:
- switch (fmax) {
- case 0x1:
- pr_alert("ACPU PVS: Fast1(L%d)\n",
- pvs_leakage);
- v1 = acpu_freq_tbl_8960_kraitv1_slow;
- v2 = acpu_freq_tbl_8960_kraitv2_fast;
- break;
- case 0x2:
- pr_alert("ACPU PVS: Fast2(L%d)\n",
- pvs_leakage);
- v1 = acpu_freq_tbl_8960_kraitv1_slow;
- v2 = acpu_freq_tbl_8960_kraitv2_fast;
- break;
- case 0x3:
- pr_alert("ACPU PVS: Fast3(L%d)\n",
- pvs_leakage);
- v1 = acpu_freq_tbl_8960_kraitv1_slow;
- v2 = acpu_freq_tbl_8960_kraitv2_f3;
- break;
- default:
- pr_info("ACPU PVS: Fast\n");
- v1 = acpu_freq_tbl_8960_kraitv1_nom_fast;
- v2 = acpu_freq_tbl_8960_kraitv2_fast;
- break;
- }
- break;
- default:
- pr_warn("ACPU PVS: Unknown. Defaulting to slow.\n");
- v1 = acpu_freq_tbl_8960_kraitv1_slow;
- v2 = acpu_freq_tbl_8960_kraitv2_slow;
- break;
+ case 0x0:
+ case 0x7:
+ case 0x1:
+ case 0x3:
+ default:
+ pr_alert("ACPU PVS: Fast\n");
+ v1 = acpu_freq_tbl_8960_kraitv1_nom_fast;
+ v2 = acpu_freq_tbl_8960_kraitv2_nom;
+ break;
}
#ifdef CONFIG_SEC_L1_DCACHE_PANIC_CHK
#if defined(CONFIG_MSM_DCVS_FOR_MSM8260A)
@@ -1795,9 +1771,11 @@ static struct acpu_level * __init select
kraitv2_apply_vmin(acpu_freq_tbl);
/* Find the max supported scaling frequency. */
- for (l = acpu_freq_tbl; l->speed.khz != 0; l++)
+ for (l = acpu_freq_tbl; l->speed.khz != 0; l++) {
if (l->use_for_scaling)
max_acpu_level = l;
+ if (l->speed.khz > 1458000) break;
+ }
BUG_ON(!max_acpu_level);
pr_info("Max ACPU freq: %u KHz\n", max_acpu_level->speed.khz);
@@ -1836,3 +1814,31 @@ struct acpuclk_soc_data acpuclk_8960_soc
struct acpuclk_soc_data acpuclk_8930_soc_data __initdata = {
.init = acpuclk_8960_init,
};
+
+#ifdef CONFIG_VDD_USERSPACE
+ssize_t acpuclk_get_vdd_levels_str(char *buf)
+{
+ int i, len = 0;
+ if (buf) {
+ mutex_lock(&driver_lock);
+ for (i = 0; acpu_freq_tbl[i].speed.khz; i++) {
+ len += sprintf(buf + len, "%8u: %4d\n", acpu_freq_tbl[i].speed.khz, acpu_freq_tbl[i].vdd_core);
+ }
+ mutex_unlock(&driver_lock);
+ }
+ return len;
+}
+
+void acpuclk_set_vdd(unsigned int khz, int vdd)
+{
+ int i;
+ mutex_lock(&driver_lock);
+ for (i = 0; acpu_freq_tbl[i].speed.khz; i++) {
+ if (khz == 0)
+ acpu_freq_tbl[i].vdd_core = min(max((unsigned int)(acpu_freq_tbl[i].vdd_core + vdd), (unsigned int)HFPLL_LOW_VDD), (unsigned int)HFPLL_HIGH_VDD);
+ else if (acpu_freq_tbl[i].speed.khz == khz)
+ acpu_freq_tbl[i].vdd_core = min(max((unsigned int)vdd, (unsigned int)HFPLL_LOW_VDD), (unsigned int)HFPLL_HIGH_VDD);
+ }
+ mutex_unlock(&driver_lock);
+}
+#endif
projects / ziggy471-sgs3-jb.git / blobdiff