From: Ziggy Date: Tue, 15 Jan 2013 18:59:35 +0000 (-0500) Subject: Initial OC X-Git-Url: https://ziggy471.com/git/gitweb.cgi?p=ziggy471-sgn2-jb.git;a=commitdiff;h=27502ce2be850dc84b3dc11f37956bcad0842822 Initial OC Signed-off-by: Ziggy --- --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -29,8 +29,14 @@ AFLAGS_sleep-exynos4.o :=$(call as-instr obj-$(CONFIG_EXYNOS5_PM) += pm-exynos5.o sleep-exynos5.o obj-$(CONFIG_CPU_FREQ) += cpufreq.o -obj-$(CONFIG_EXYNOS4_CPUFREQ) += asv.o asv-4210.o asv-4x12.o -obj-$(CONFIG_EXYNOS4_CPUFREQ) += cpufreq-4210.o cpufreq-4x12.o +obj-$(CONFIG_EXYNOS4_CPUFREQ) += asv.o +ifeq ($(CONFIG_CPU_EXYNOS4210),y) +obj-$(CONFIG_EXYNOS4_CPUFREQ) += asv-4210.o +obj-$(CONFIG_EXYNOS4_CPUFREQ) += cpufreq-4210.o +else +obj-$(CONFIG_EXYNOS4_CPUFREQ) += asv-4x12.o +obj-$(CONFIG_EXYNOS4_CPUFREQ) += cpufreq-4x12.o +endif obj-$(CONFIG_EXYNOS5_CPUFREQ) += asv.o asv-5250.o obj-$(CONFIG_EXYNOS5_CPUFREQ) += cpufreq-5250.o obj-$(CONFIG_EXYNOS4_CPUIDLE) += cpuidle-exynos4.o idle-exynos4.o --- a/arch/arm/mach-exynos/busfreq_opp_4x12.c +++ b/arch/arm/mach-exynos/busfreq_opp_4x12.c @@ -49,7 +49,7 @@ #include #include -#define UP_THRESHOLD 30 +#define UP_THRESHOLD 23 #define IDLE_THRESHOLD 4 #define UP_CPU_THRESHOLD 11 #define MAX_CPU_THRESHOLD 20 --- a/arch/arm/mach-exynos/clock-exynos4212.c +++ b/arch/arm/mach-exynos/clock-exynos4212.c @@ -976,13 +976,23 @@ static struct vpll_div_data vpll_div_421 {54000000, 2, 72, 4, 0, 0, 0, 0}, {108000000, 2, 72, 3, 0, 0, 0, 0}, {160000000, 3, 160, 3, 0, 0, 0, 0}, + {200000000, 3, 200, 3, 0, 0, 0, 0}, {266000000, 3, 133, 2, 0, 0, 0, 0}, {275000000, 2, 92, 2, 43692, 0, 0, 0}, {300000000, 2, 100, 2, 0, 0, 0, 0}, {333000000, 2, 111, 2, 0, 0, 0, 0}, {350000000, 3, 175, 2, 0, 0, 0, 0}, + {400000000, 3, 100, 1, 0, 0, 0, 0}, {440000000, 3, 110, 1, 0, 0, 0, 0}, + {500000000, 2, 166, 2, 0, 0, 0, 0}, {533000000, 3, 133, 1, 16384, 0, 0, 0}, + {600000000, 2, 100, 1, 0, 0, 0, 0}, + {640000000, 3, 160, 1, 0, 0, 0, 0}, + {666000000, 2, 111, 1, 0, 0, 0, 0}, + {700000000, 3, 175, 1, 0, 0, 0, 0}, + {733000000, 2, 122, 1, 0, 0, 0, 0}, + {750000000, 2, 125, 1, 0, 0, 0, 0}, + {800000000, 2, 133, 1, 0, 0, 0, 0}, }; static unsigned long exynos4212_vpll_get_rate(struct clk *clk) --- a/arch/arm/mach-exynos/cpufreq-4x12.c +++ b/arch/arm/mach-exynos/cpufreq-4x12.c @@ -26,7 +26,7 @@ #include #include -#define CPUFREQ_LEVEL_END (L14 + 1) +#define CPUFREQ_LEVEL_END (L17 + 1) #undef PRINT_DIV_VAL @@ -46,24 +46,27 @@ struct cpufreq_clkdiv { unsigned int clkdiv1; }; -static unsigned int exynos4x12_volt_table[CPUFREQ_LEVEL_END]; +unsigned int exynos4x12_volt_table[CPUFREQ_LEVEL_END]; static struct cpufreq_frequency_table exynos4x12_freq_table[] = { - {L0, 1600*1000}, - {L1, 1500*1000}, - {L2, 1400*1000}, - {L3, 1300*1000}, - {L4, 1200*1000}, - {L5, 1100*1000}, - {L6, 1000*1000}, - {L7, 900*1000}, - {L8, 800*1000}, - {L9, 700*1000}, - {L10, 600*1000}, - {L11, 500*1000}, - {L12, 400*1000}, - {L13, 300*1000}, - {L14, 200*1000}, + {L0, 1920*1000}, + {L1, 1800*1000}, + {L2, 1704*1000}, + {L3, 1600*1000}, + {L4, 1500*1000}, + {L5, 1400*1000}, + {L6, 1300*1000}, + {L7, 1200*1000}, + {L8, 1100*1000}, + {L9, 1000*1000}, + {L10, 900*1000}, + {L11, 800*1000}, + {L12, 700*1000}, + {L13, 600*1000}, + {L14, 500*1000}, + {L15, 400*1000}, + {L16, 300*1000}, + {L17, 200*1000}, {0, CPUFREQ_TABLE_END}, }; @@ -127,49 +130,59 @@ static unsigned int clkdiv_cpu0_4412[CPU * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH, * DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 } */ - /* ARM L0: 1600Mhz */ - { 0, 3, 7, 0, 6, 1, 7, 0 }, - /* ARM L1: 1500Mhz */ + /* ARM L0: 1920Mhz */ + { 0, 4, 7, 0, 7, 1, 7, 0 }, + + /* ARM L1: 1800Mhz */ + { 0, 4, 7, 0, 7, 1, 7, 0 }, + + /* ARM L2: 1700Mhz */ + { 0, 4, 7, 0, 7, 1, 7, 0 }, + + /* ARM L3: 1600Mhz */ + { 0, 4, 7, 0, 6, 1, 7, 0 }, + + /* ARM L4: 1500Mhz */ { 0, 3, 7, 0, 6, 1, 7, 0 }, - /* ARM L2: 1400Mhz */ + /* ARM L5: 1400Mhz */ { 0, 3, 7, 0, 6, 1, 6, 0 }, - /* ARM L3: 1300Mhz */ + /* ARM L6: 1300Mhz */ { 0, 3, 7, 0, 5, 1, 6, 0 }, - /* ARM L4: 1200Mhz */ + /* ARM L7: 1200Mhz */ { 0, 3, 7, 0, 5, 1, 5, 0 }, - /* ARM L5: 1100MHz */ + /* ARM L8: 1100MHz */ { 0, 3, 6, 0, 4, 1, 5, 0 }, - /* ARM L6: 1000MHz */ + /* ARM L9: 1000MHz */ { 0, 2, 5, 0, 4, 1, 4, 0 }, - /* ARM L7: 900MHz */ + /* ARM L10: 900MHz */ { 0, 2, 5, 0, 3, 1, 4, 0 }, - /* ARM L8: 800MHz */ + /* ARM L11: 800MHz */ { 0, 2, 5, 0, 3, 1, 3, 0 }, - /* ARM L9: 700MHz */ + /* ARM L12: 700MHz */ { 0, 2, 4, 0, 3, 1, 3, 0 }, - /* ARM L10: 600MHz */ + /* ARM L13: 600MHz */ { 0, 2, 4, 0, 3, 1, 2, 0 }, - /* ARM L11: 500MHz */ + /* ARM L14: 500MHz */ { 0, 2, 4, 0, 3, 1, 2, 0 }, - /* ARM L12: 400MHz */ + /* ARM L15: 400MHz */ { 0, 2, 4, 0, 3, 1, 1, 0 }, - /* ARM L13: 300MHz */ + /* ARM L16: 300MHz */ { 0, 2, 4, 0, 2, 1, 1, 0 }, - /* ARM L14: 200MHz */ + /* ARM L17: 200MHz */ { 0, 1, 3, 0, 1, 1, 1, 0 }, }; @@ -227,96 +240,115 @@ static unsigned int clkdiv_cpu1_4412[CPU /* Clock divider value for following * { DIVCOPY, DIVHPM, DIVCORES } */ - /* ARM L0: 1600MHz */ + + /* ARM L0: 1920MHz */ + { 7, 0, 7 }, + + /* ARM L1: 1800MHz */ + { 7, 0, 7 }, + + /* ARM L2: 1700MHz */ + { 7, 0, 7 }, + + /* ARM L3: 1600MHz */ { 6, 0, 7 }, - /* ARM L1: 1500MHz */ + /* ARM L4: 1500MHz */ { 6, 0, 7 }, - /* ARM L2: 1400MHz */ + /* ARM L5: 1400MHz */ { 6, 0, 6 }, - /* ARM L3: 1300MHz */ + /* ARM L6: 1300MHz */ { 5, 0, 6 }, - /* ARM L4: 1200MHz */ + /* ARM L7: 1200MHz */ { 5, 0, 5 }, - /* ARM L5: 1100MHz */ + /* ARM L8: 1100MHz */ { 4, 0, 5 }, - /* ARM L6: 1000MHz */ + /* ARM L9: 1000MHz */ { 4, 0, 4 }, - /* ARM L7: 900MHz */ + /* ARM L10: 900MHz */ { 3, 0, 4 }, - /* ARM L8: 800MHz */ + /* ARM L11: 800MHz */ { 3, 0, 3 }, - /* ARM L9: 700MHz */ + /* ARM L12: 700MHz */ { 3, 0, 3 }, - /* ARM L10: 600MHz */ + /* ARM L13: 600MHz */ { 3, 0, 2 }, - /* ARM L11: 500MHz */ + /* ARM L14: 500MHz */ { 3, 0, 2 }, - /* ARM L12: 400MHz */ + /* ARM L15: 400MHz */ { 3, 0, 1 }, - /* ARM L13: 300MHz */ + /* ARM L16: 300MHz */ { 3, 0, 1 }, - /* ARM L14: 200MHz */ + /* ARM L17: 200MHz */ { 3, 0, 0 }, }; static unsigned int exynos4x12_apll_pms_table[CPUFREQ_LEVEL_END] = { - /* APLL FOUT L0: 1600MHz */ + /* APLL FOUT L0: 1920MHz */ + ((240<<16)|(3<<8)|(0x0)), + + /* APLL FOUT L1: 1800MHz */ + ((300<<16)|(4<<8)|(0x0)), + + /* APLL FOUT L2: 1704MHz */ + ((213<<16)|(3<<8)|(0x0)), + + /* APLL FOUT L3: 1600MHz */ ((200<<16)|(3<<8)|(0x0)), - /* APLL FOUT L1: 1500MHz */ + /* APLL FOUT L4: 1500MHz */ ((250<<16)|(4<<8)|(0x0)), - /* APLL FOUT L2: 1400MHz */ + /* APLL FOUT L5: 1400MHz */ ((175<<16)|(3<<8)|(0x0)), - /* APLL FOUT L3: 1300MHz */ + /* APLL FOUT L6: 1300MHz */ ((325<<16)|(6<<8)|(0x0)), - /* APLL FOUT L4: 1200MHz */ + /* APLL FOUT L7: 1200MHz */ ((200<<16)|(4<<8)|(0x0)), - /* APLL FOUT L5: 1100MHz */ + /* APLL FOUT L8: 1100MHz */ ((275<<16)|(6<<8)|(0x0)), - /* APLL FOUT L6: 1000MHz */ + /* APLL FOUT L9: 1000MHz */ ((125<<16)|(3<<8)|(0x0)), - /* APLL FOUT L7: 900MHz */ + /* APLL FOUT L10: 900MHz */ ((150<<16)|(4<<8)|(0x0)), - /* APLL FOUT L8: 800MHz */ + /* APLL FOUT L11: 800MHz */ ((100<<16)|(3<<8)|(0x0)), - /* APLL FOUT L9: 700MHz */ + /* APLL FOUT L12: 700MHz */ ((175<<16)|(3<<8)|(0x1)), - /* APLL FOUT L10: 600MHz */ + /* APLL FOUT L13: 600MHz */ ((200<<16)|(4<<8)|(0x1)), - /* APLL FOUT L11: 500MHz */ + /* APLL FOUT L14: 500MHz */ ((125<<16)|(3<<8)|(0x1)), - /* APLL FOUT L12 400MHz */ + /* APLL FOUT L15 400MHz */ ((100<<16)|(3<<8)|(0x1)), - /* APLL FOUT L13: 300MHz */ + /* APLL FOUT L16: 300MHz */ ((200<<16)|(4<<8)|(0x2)), - /* APLL FOUT L14: 200MHz */ + /* APLL FOUT L17: 200MHz */ ((100<<16)|(3<<8)|(0x2)), }; @@ -325,7 +357,7 @@ static unsigned int exynos4x12_apll_pms_ * ASV group voltage table */ -#define NO_ABB_LIMIT L8 +#define NO_ABB_LIMIT L14 static const unsigned int asv_voltage_4212[CPUFREQ_LEVEL_END][12] = { /* ASV0, ASV1, ASV2, ASV3, ASV4, ASV5, ASV6, ASV7, ASV8, ASV9, ASV10, ASV11 */ @@ -351,63 +383,50 @@ static const unsigned int asv_voltage_s[ 1050000, 1025000, 1000000, 1000000, 1000000, 950000, 950000 }; -/* ASV table for 12.5mV step */ +/* 20120210 DVFS table version */ static const unsigned int asv_voltage_step_12_5[CPUFREQ_LEVEL_END][12] = { /* ASV0, ASV1, ASV2, ASV3, ASV4, ASV5, ASV6, ASV7, ASV8, ASV9, ASV10, ASV11 */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L0 - Not used */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L1 - Not used */ - { 1325000, 1312500, 1300000, 1287500, 1300000, 1287500, 1275000, 1250000, 1250000, 1237500, 1225000, 1212500 }, - { 1300000, 1275000, 1237500, 1237500, 1250000, 1250000, 1237500, 1212500, 1200000, 1200000, 1187500, 1175000 }, - { 1225000, 1212500, 1200000, 1187500, 1200000, 1187500, 1175000, 1150000, 1137500, 1125000, 1125000, 1112500 }, - { 1175000, 1162500, 1150000, 1137500, 1150000, 1137500, 1125000, 1100000, 1100000, 1075000, 1075000, 1062500 }, - { 1125000, 1112500, 1100000, 1087500, 1100000, 1087500, 1075000, 1050000, 1037500, 1025000, 1025000, 1012500 }, - { 1075000, 1062500, 1050000, 1050000, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 987500, 975000 }, - { 1037500, 1025000, 1000000, 1000000, 1000000, 987500, 975000, 962500, 962500, 962500, 962500, 950000 }, - { 1012500, 1000000, 975000, 975000, 975000, 975000, 962500, 962500, 950000, 950000, 950000, 937500 }, - { 1000000, 987500, 962500, 962500, 962500, 962500, 950000, 950000, 937500, 937500, 937500, 925000 }, - { 987500, 975000, 950000, 937500, 950000, 937500, 937500, 937500, 912500, 912500, 912500, 900000 }, - { 975000, 962500, 950000, 925000, 950000, 925000, 925000, 925000, 900000, 900000, 900000, 887500 }, - { 950000, 937500, 925000, 900000, 925000, 900000, 900000, 900000, 900000, 887500, 875000, 862500 }, - { 925000, 912500, 900000, 900000, 900000, 900000, 900000, 900000, 887500, 875000, 875000, 862500 }, + { 1425000, 1425000, 1425000, 1425000, 1425000, 1425000, 1425000, 1425000, 1425000, 1425000, 1425000, 1425000 }, /* L0 1920MHz */ + { 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000 }, /* L1 1800MHz */ + { 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1387500, 1375000, 1362500 }, /* L2 1700MHz */ + { 1400000, 1400000, 1400000, 1400000, 1387500, 1387500, 1375000, 1362500, 1350000, 1337500, 1325000, 1312500 }, /* L3 1600MHz */ + { 1387500, 1375000, 1362500, 1350000, 1337500, 1325000, 1312500, 1300000, 1287500, 1275000, 1262500, 1250000 }, /* L4 1500MHz */ + { 1325000, 1312500, 1300000, 1287500, 1300000, 1287500, 1275000, 1250000, 1250000, 1237500, 1225000, 1212500 }, /* L5 1400MHz */ + { 1300000, 1275000, 1237500, 1237500, 1250000, 1250000, 1237500, 1212500, 1200000, 1200000, 1187500, 1175000 }, /* L6 1300MHz */ + { 1225000, 1212500, 1200000, 1187500, 1200000, 1187500, 1175000, 1150000, 1137500, 1125000, 1125000, 1112500 }, /* L7 1200MHz */ + { 1175000, 1162500, 1150000, 1137500, 1150000, 1137500, 1125000, 1100000, 1100000, 1075000, 1075000, 1062500 }, /* L8 1100MHz */ + { 1125000, 1112500, 1100000, 1087500, 1100000, 1087500, 1075000, 1050000, 1037500, 1025000, 1025000, 1012500 }, /* L9 1000MHz */ + { 1075000, 1062500, 1050000, 1050000, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 987500, 975000 }, /* L10 900MHz */ + { 1037500, 1025000, 1000000, 1000000, 1000000, 987500, 975000, 962500, 962500, 962500, 962500, 950000 }, /* L11 800MHz */ + { 1012500, 1000000, 975000, 975000, 975000, 975000, 962500, 962500, 950000, 950000, 950000, 937500 }, /* L12 700MHz */ + { 1000000, 987500, 962500, 962500, 962500, 962500, 950000, 950000, 937500, 937500, 937500, 925000 }, /* L13 600MHz */ + { 987500, 975000, 950000, 937500, 950000, 937500, 937500, 937500, 912500, 912500, 912500, 900000 }, /* L14 500MHz */ + { 975000, 962500, 950000, 925000, 950000, 925000, 925000, 925000, 900000, 900000, 900000, 887500 }, /* L15 400MHz */ + { 950000, 937500, 925000, 900000, 925000, 900000, 900000, 900000, 900000, 887500, 875000, 862500 }, /* L16 300MHz */ + { 925000, 912500, 900000, 900000, 900000, 900000, 900000, 900000, 887500, 875000, 875000, 862500 }, /* L17 200MHz */ }; -/* 20120927 DVFS table for pega prime */ +/* 20120725 DVFS table for pega prime */ static const unsigned int asv_voltage_step_12_5_rev2[CPUFREQ_LEVEL_END][13] = { /* ASV0, ASV1, ASV2, ASV3, ASV4, ASV5, ASV6, ASV7, ASV8, ASV9, ASV10, ASV11 ASV12 */ - { 1312500, 1312500, 1312500, 1312500, 1300000, 1287500, 1275000, 1262500, 1250000, 1237500, 1212500, 1200000, 1187500 }, /* L0 */ - { 1312500, 1262500, 1262500, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000, 1187500, 1162500, 1150000, 1137500 }, /* L1 */ - { 1275000, 1225000, 1225000, 1225000, 1212500, 1200000, 1187500, 1175000, 1162500, 1150000, 1125000, 1112500, 1100000 }, /* L2 */ - { 1225000, 1175000, 1175000, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, 1075000, 1062500, 1050000 }, /* L3 */ - { 1187500, 1137500, 1137500, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, 1037500, 1025000, 1012500 }, /* L4 */ - { 1150000, 1100000, 1100000, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1000000, 987500, 975000 }, /* L5 */ - { 1125000, 1075000, 1075000, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 975000, 962500, 950000 }, /* L6 */ - { 1100000, 1050000, 1050000, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 975000, 950000, 937500, 925000 }, /* L7 */ - { 1062500, 1012500, 1012500, 1012500, 1000000, 987500, 975000, 962500, 950000, 937500, 912500, 900000, 887500 }, /* L8 */ - { 1037500, 987500, 987500, 987500, 975000, 962500, 950000, 937500, 925000, 912500, 887500, 887500, 887500 }, /* L9 */ - { 1012500, 962500, 962500, 962500, 950000, 937500, 925000, 912500, 900000, 887500, 875000, 875000, 875000 }, /* L10 */ - { 1000000, 950000, 950000, 950000, 937500, 925000, 912500, 900000, 887500, 887500, 875000, 875000, 875000 }, /* L11 */ - { 987500, 937500, 937500, 937500, 925000, 912500, 900000, 887500, 887500, 887500, 875000, 875000, 875000 }, /* L12 */ - { 975000, 925000, 925000, 925000, 912500, 900000, 887500, 887500, 887500, 887500, 875000, 875000, 875000 }, /* L13 */ - { 962500, 912500, 912500, 912500, 900000, 887500, 887500, 887500, 887500, 887500, 875000, 875000, 875000 }, /* L14 */ -}; - -static const unsigned int asv_voltage_step_1ghz[CPUFREQ_LEVEL_END][12] = { - /* ASV0, ASV1, ASV2, ASV3, ASV4, ASV5, ASV6, ASV7, ASV8, ASV9, ASV10, ASV11 */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L0 - Not used */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L1 - Not used */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L2 - Not used */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L3 - Not used */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L4 - Not used */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* L5 - Not used */ - { 1200000, 1200000, 1200000, 1200000, 1125000, 1125000, 1125000, 1075000, 1075000, 1075000, 1075000, 1037500 }, - { 1150000, 1150000, 1150000, 1150000, 1075000, 1075000, 1075000, 1037500, 1037500, 1037500, 1037500, 1000000 }, - { 1100000, 1100000, 1100000, 1100000, 1025000, 1025000, 1025000, 987500, 987500, 987500, 987500, 975000 }, - { 1050000, 1050000, 1050000, 1050000, 1000000, 1000000, 1000000, 987500, 987500, 987500, 987500, 962500 }, - { 1025000, 1025000, 1025000, 1025000, 987500, 987500, 987500, 975000, 975000, 975000, 975000, 950000 }, - { 1000000, 1000000, 1000000, 1000000, 975000, 975000, 975000, 962500, 962500, 962500, 962500, 925000 }, - { 1000000, 1000000, 1000000, 1000000, 975000, 975000, 975000, 950000, 950000, 950000, 950000, 912500 }, - { 975000, 975000, 975000, 975000, 950000, 950000, 950000, 925000, 925000, 925000, 925000, 887500 }, - { 975000, 975000, 975000, 975000, 937500, 937500, 937500, 925000, 925000, 925000, 925000, 887500 }, + { 1425000, 1425000, 1425000, 1425000, 1425000, 1425000, 1425000, 1425000, 1425000, 1425000, 1425000, 1425000, 1425000}, /* L0 1920MHz */ + { 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000}, /* L1 1800MHz */ + { 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1400000, 1387500, 1375000, 1362500, 1350000}, /* L2 1700MHz */ + { 1312500, 1312500, 1312500, 1312500, 1300000, 1287500, 1275000, 1262500, 1250000, 1237500, 1212500, 1200000, 1187500 }, /* L3 1600MHz */ + { 1275000, 1262500, 1262500, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000, 1187500, 1162500, 1150000, 1137500 }, /* L4 1500MHz */ + { 1237500, 1225000, 1225000, 1225000, 1212500, 1200000, 1187500, 1175000, 1162500, 1150000, 1125000, 1112500, 1100000 }, /* L5 1400MHz */ + { 1187500, 1175000, 1175000, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, 1075000, 1062500, 1050000 }, /* L6 1300MHz */ + { 1150000, 1137500, 1137500, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, 1037500, 1025000, 1012500 }, /* L7 1200MHz */ + { 1112500, 1100000, 1100000, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1000000, 987500, 975000 }, /* L8 1100MHz */ + { 1087500, 1075000, 1075000, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 975000, 962500, 950000 }, /* L9 1000MHz */ + { 1062500, 1050000, 1050000, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 975000, 950000, 937500, 925000 }, /* L10 900MHz */ + { 1025000, 1012500, 1012500, 1012500, 1000000, 987500, 975000, 962500, 950000, 937500, 912500, 900000, 887500 }, /* L11 800MHz */ + { 1000000, 987500, 987500, 987500, 975000, 962500, 950000, 937500, 925000, 912500, 887500, 887500, 887500 }, /* L12 700MHz */ + { 975000, 962500, 962500, 962500, 950000, 937500, 925000, 912500, 900000, 887500, 875000, 875000, 875000 }, /* L13 600MHz */ + { 962500, 950000, 950000, 950000, 937500, 925000, 912500, 900000, 887500, 887500, 875000, 875000, 875000 }, /* L14 500MHz */ + { 950000, 937500, 937500, 937500, 925000, 912500, 900000, 887500, 887500, 887500, 875000, 875000, 875000 }, /* L15 400MHz */ + { 937500, 925000, 925000, 925000, 912500, 900000, 887500, 887500, 887500, 887500, 875000, 875000, 875000 }, /* L16 300MHz */ + { 925000, 912500, 912500, 912500, 900000, 887500, 887500, 887500, 887500, 887500, 875000, 875000, 875000 }, /* L17 200MHz */ }; static void set_clkdiv(unsigned int div_index) @@ -566,9 +585,8 @@ static void exynos4x12_set_frequency(uns } /* ABB value is changed in below case */ - if (soc_is_exynos4412() && (exynos_result_of_asv > 3) - && (samsung_rev() < EXYNOS4412_REV_2_0)) { - if (new_index == L14) + if (soc_is_exynos4412() && (exynos_result_of_asv > 3)) { + if (new_index == L18) exynos4x12_set_abb_member(ABB_ARM, ABB_MODE_100V); else exynos4x12_set_abb_member(ABB_ARM, ABB_MODE_130V); @@ -576,32 +594,11 @@ static void exynos4x12_set_frequency(uns } /* Get maximum cpufreq index of chip */ -static unsigned int get_max_cpufreq_idx(void) -{ - unsigned int index; - - /* exynos4x12 prime supports 1.6GHz */ - if (samsung_rev() >= EXYNOS4412_REV_2_0) - index = L0; - else { - /* exynos4x12 supports only 1.4GHz and 1.1GHz */ - if (exynos_armclk_max != 1400000) - index = L6; - else - index = L2; - } - - return index; -} - static void __init set_volt_table(void) { unsigned int i, tmp; - max_support_idx = get_max_cpufreq_idx(); - - for (i = 0; i < max_support_idx; i++) - exynos4x12_freq_table[i].frequency = CPUFREQ_ENTRY_INVALID; + max_support_idx = L0; pr_info("DVFS : VDD_ARM Voltage table set with %d Group\n", exynos_result_of_asv); @@ -618,17 +615,11 @@ static void __init set_volt_table(void) for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++) exynos4x12_volt_table[i] = asv_voltage_step_12_5_rev2[i][exynos_result_of_asv]; - } else { - if (exynos_armclk_max == 1000000) { - for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++) - exynos4x12_volt_table[i] = - asv_voltage_step_1ghz[i][exynos_result_of_asv]; } else { for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++) exynos4x12_volt_table[i] = asv_voltage_step_12_5[i][exynos_result_of_asv]; } - } } else { pr_err("%s: Can't find SoC type \n", __func__); } @@ -679,10 +670,10 @@ static void __init set_volt_table(void) */ #ifdef CONFIG_SLP static struct dvfs_qos_info exynos4x12_dma_lat_qos[] = { - { 118, 200000, L14 }, - { 40, 500000, L11 }, - { 24, 800000, L8 }, - { 16, 1000000, L6 }, + { 118, 200000, L19 }, + { 40, 500000, L16 }, + { 24, 800000, L13 }, + { 16, 1000000, L11 }, {}, }; #endif @@ -771,7 +762,7 @@ int exynos4x12_cpufreq_init(struct exyno info->mpll_freq_khz = rate; #ifdef CONFIG_SLP /* S-Boot at 20120406 uses L8 at bootup */ - info->pm_lock_idx = L8; + info->pm_lock_idx = L11; /* * However, the bootup frequency might get changed anytime. @@ -788,7 +779,7 @@ int exynos4x12_cpufreq_init(struct exyno pr_info("Bootup CPU Frequency = [%d] %dMHz\n", info->pm_lock_idx, rate / 1000); #else - info->pm_lock_idx = L6; + info->pm_lock_idx = L9; #endif /* * ARM clock source will be changed APLL to MPLL temporary @@ -798,9 +789,9 @@ int exynos4x12_cpufreq_init(struct exyno * So, pll_safe_idx set to value based on MPLL clock.(800MHz or 880MHz) */ if (samsung_rev() >= EXYNOS4412_REV_2_0) - info->pll_safe_idx = L7; + info->pll_safe_idx = L10; else - info->pll_safe_idx = L8; + info->pll_safe_idx = L11; info->max_support_idx = max_support_idx; info->min_support_idx = min_support_idx; @@ -838,3 +829,52 @@ err_moutcore: return -EINVAL; } EXPORT_SYMBOL(exynos4x12_cpufreq_init); + + +#ifdef CONFIG_VDD_USERSPACE +ssize_t show_vdd_levels(struct cpufreq_policy *policy, char *buf) { + int i, len = 0; + if (buf) + { + for (i = exynos_info->max_support_idx; i<=exynos_info->min_support_idx; i++) + { + if(exynos_info->freq_table[i].frequency==CPUFREQ_ENTRY_INVALID) continue; + len += sprintf(buf + len, "%dmhz: %d mV\n", + exynos_info->freq_table[i].frequency/1000, + exynos_info->volt_table[i] % 500 + exynos_info->volt_table[i]); + } + } + return len; +} + +ssize_t store_vdd_levels(struct cpufreq_policy *policy, + const char *buf, size_t count) { + + unsigned int ret = -EINVAL; + int i = 0; + int t[14]; + + ret = sscanf(buf, "%d %d %d %d %d %d %d %d %d %d %d %d %d %d", + &t[0],&t[1],&t[2],&t[3],&t[4],&t[5],&t[6],&t[7],&t[8],&t[9],&t[10],&t[11],&t[12],&t[13]); + + if(ret != 14) { + return -EINVAL; + } else { + int invalid_offset = 0; + + for (i = 0; i < 18; i++) { + if (t[i] > CONFIG_CPU_FREQ_MAX_VDD) + t[i] = CONFIG_CPU_FREQ_MAX_VDD; + else if (t[i] < CONFIG_CPU_FREQ_MIN_VDD) + t[i] = CONFIG_CPU_FREQ_MIN_VDD; + + while(exynos_info->freq_table[i+invalid_offset].frequency==CPUFREQ_ENTRY_INVALID) + ++invalid_offset; + + exynos_info->volt_table[i+invalid_offset] = t[i]; + } + } + return count; +} + +#endif // CONFIG_VDD_USERSPACE --- a/arch/arm/mach-exynos/cpufreq.c +++ b/arch/arm/mach-exynos/cpufreq.c @@ -714,7 +714,7 @@ static int exynos_cpufreq_cpu_init(struc cpufreq_frequency_table_get_attr(exynos_info->freq_table, policy->cpu); /* set the transition latency value */ - policy->cpuinfo.transition_latency = 100000; + policy->cpuinfo.transition_latency = 11000; /* * EXYNOS4 multi-core processors has 2 cores @@ -749,6 +749,11 @@ static struct notifier_block exynos_cpuf .notifier_call = exynos_cpufreq_reboot_notifier_call, }; +static struct freq_attr *exynos_cpufreq_attr[] = { + &cpufreq_freq_attr_scaling_available_freqs, + NULL, +}; + static struct cpufreq_driver exynos_driver = { .flags = CPUFREQ_STICKY, .verify = exynos_verify_speed, @@ -756,6 +761,7 @@ static struct cpufreq_driver exynos_driv .get = exynos_getspeed, .init = exynos_cpufreq_cpu_init, .name = "exynos_cpufreq", + .attr = exynos_cpufreq_attr, #ifdef CONFIG_PM .suspend = exynos_cpufreq_suspend, .resume = exynos_cpufreq_resume, --- a/arch/arm/mach-exynos/subsystem_restart.c +++ b/arch/arm/mach-exynos/subsystem_restart.c @@ -228,11 +228,13 @@ int subsystem_restart(const char *subsys subsys->ongoing = true; +#ifdef CONFIG_DEBUG_FS /* check debug level */ if (!sec_debug_level.uint_val) { /* debug level is low, set mdm_dump to Zero */ mdm_dump = 0; } +#endif data = kzalloc(sizeof(struct restart_wq_data), GFP_KERNEL); if (!data) { --- a/drivers/cpufreq/Kconfig +++ b/drivers/cpufreq/Kconfig @@ -17,6 +17,16 @@ config CPU_FREQ if CPU_FREQ +config CPU_FREQ_MAX_VDD + int "Max CPU VDD uV" + depends on CPU_FREQ + default 1500000 + +config CPU_FREQ_MIN_VDD + int "Min CPU VDD uV" + depends on CPU_FREQ + default 600000 + config CPU_FREQ_TABLE tristate @@ -457,6 +467,13 @@ config CPU_FREQ_DVFS_MONITOR This option adds a proc node for dvfs monitoring. /proc/dvfs_mon +config VDD_USERSPACE + bool "VDD sysfs interface" + default n + depends on CPU_FREQ_STAT + help + exposes the VDD table to userspace + allows users to adjust voltages on the fly menu "x86 CPU frequency scaling drivers" depends on X86 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -568,6 +568,11 @@ static ssize_t show_bios_limit(struct cp return sprintf(buf, "%u\n", policy->cpuinfo.max_freq); } +#ifdef CONFIG_VDD_USERSPACE +extern ssize_t store_vdd_levels(struct cpufreq_policy *policy, const char *buf, size_t count); +extern ssize_t show_vdd_levels(struct cpufreq_policy *policy, char *buf); +#endif // CONFIG_VDD_USERSPACE + cpufreq_freq_attr_ro_perm(cpuinfo_cur_freq, 0400); cpufreq_freq_attr_ro(cpuinfo_min_freq); cpufreq_freq_attr_ro(cpuinfo_max_freq); @@ -583,6 +588,10 @@ cpufreq_freq_attr_rw(scaling_max_freq); cpufreq_freq_attr_rw(scaling_governor); cpufreq_freq_attr_rw(scaling_setspeed); +#ifdef CONFIG_VDD_USERSPACE +define_one_global_rw(vdd_levels); +#endif // CONFIG_VDD_USERSPACE + static struct attribute *default_attrs[] = { &cpuinfo_min_freq.attr, &cpuinfo_max_freq.attr, @@ -598,6 +607,18 @@ static struct attribute *default_attrs[] NULL }; +#ifdef CONFIG_VDD_USERSPACE +static struct attribute *vddtbl_attrs[] = { + &vdd_levels.attr, + NULL +}; + +static struct attribute_group vddtbl_attr_group = { + .attrs = vddtbl_attrs, + .name = "vdd_table", +}; +#endif /* CONFIG_VDD_USERSPACE */ + struct kobject *cpufreq_global_kobject; EXPORT_SYMBOL(cpufreq_global_kobject); @@ -1881,6 +1902,9 @@ EXPORT_SYMBOL_GPL(cpufreq_unregister_dri static int __init cpufreq_core_init(void) { int cpu; +#ifdef CONFIG_VDD_USERSPACE + int rc; +#endif /* CONFIG_VDD_USERSPACE */ for_each_possible_cpu(cpu) { per_cpu(cpufreq_policy_cpu, cpu) = -1; @@ -1892,6 +1916,10 @@ static int __init cpufreq_core_init(void BUG_ON(!cpufreq_global_kobject); register_syscore_ops(&cpufreq_syscore_ops); +#ifdef CONFIG_VDD_USERSPACE + rc = sysfs_create_group(cpufreq_global_kobject, &vddtbl_attr_group); +#endif /* CONFIG_VDD_USERSPACE */ + return 0; } core_initcall(cpufreq_core_init);