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SCHEDULER: set define LOAD_FREQ to (4*HZ+61)

/drivers/staging/tidspbridge/rmgr

-rw-r--r--	dbdcd.c	blob \| history
-rw-r--r--	disp.c	blob \| history
-rw-r--r--	drv.c	blob \| history
-rw-r--r--	drv_interface.c	blob \| history
-rw-r--r--	drv_interface.h	blob \| history
-rw-r--r--	dspdrv.c	blob \| history
-rw-r--r--	mgr.c	blob \| history
-rw-r--r--	nldr.c	blob \| history
-rw-r--r--	node.c	blob \| history
-rw-r--r--	proc.c	blob \| history
-rw-r--r--	pwr.c	blob \| history
-rw-r--r--	rmm.c	blob \| history
-rw-r--r--	strm.c	blob \| history

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