--- a/arch/arm/mach-msm/acpuclock-8960.c
+++ b/arch/arm/mach-msm/acpuclock-8960.c
@@ -511,7 +511,7 @@ static struct acpu_level acpu_freq_tbl_8
{ 1, { 1404000, HFPLL, 1, 0, 0x34 }, L2(19), 1237500 },
{ 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(20), 1237500 },
{ 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(21), 1250000 },
- { 1, { 1674000, HFPLL, 1, 0, 0x3A }, L2(22), 1250000 },
+ { 1, { 1674000, HFPLL, 1, 0, 0x3A }, L2(22), 1275000 },
{ 1, { 1728000, HFPLL, 1, 0, 0x3C }, L2(23), 1262500 },
{ 1, { 1809000, HFPLL, 1, 0, 0x3E }, L2(21), 1262500 },
{ 1, { 1890000, HFPLL, 1, 0, 0x40 }, L2(21), 1300000 },
@@ -547,7 +547,7 @@ static struct acpu_level acpu_freq_tbl_8
{ 1, { 1674000, HFPLL, 1, 0, 0x3A }, L2(22), 1200000 },
{ 1, { 1728000, HFPLL, 1, 0, 0x3C }, L2(23), 1250000 },
{ 1, { 1809000, HFPLL, 1, 0, 0x3E }, L2(21), 1275000 },
- { 1, { 1900000, HFPLL, 1, 0, 0x40 }, L2(21), 1300000 },
+ { 1, { 1900000, HFPLL, 1, 0, 0x40 }, L2(21), 1325000 },
{ 1, { 1998000, HFPLL, 1, 0, 0x42 }, L2(20), 1325000 },
{ 1, { 2106000, HFPLL, 1, 0, 0x44 }, L2(20), 1350000 },
{ 0, { 0 } }
@@ -1225,7 +1225,7 @@ static void __init hfpll_init(struct sca
}
/* Voltage regulator initialization. */
-static void regulator_init(int set_vdd)
+static void __init regulator_init(int set_vdd)
{
int cpu, ret;
struct scalable *sc;
@@ -1256,7 +1256,7 @@ static void regulator_init(int set_vdd)
}
/* Set initial rate for a given core. */
-static void init_clock_sources(struct scalable *sc,
+static void __init init_clock_sources(struct scalable *sc,
struct core_speed *tgt_s)
{
uint32_t regval;
@@ -1286,7 +1286,7 @@ static void init_clock_sources(struct sc
sc->first_set_call = true;
}
-static void per_cpu_init(void *data)
+static void __init per_cpu_init(void *data)
{
struct acpu_level *max_acpu_level = data;
int cpu = smp_processor_id();
@@ -1314,7 +1314,7 @@ static void __init bus_init(unsigned int
#ifdef CONFIG_CPU_FREQ_MSM
static struct cpufreq_frequency_table freq_table[NR_CPUS][FREQ_TABLE_SIZE];
-static void cpufreq_table_init(void)
+static void __init cpufreq_table_init(void)
{
int cpu;
--- a/arch/arm/mach-msm/board-8960-display.c
+++ b/arch/arm/mach-msm/board-8960-display.c
@@ -1442,6 +1442,16 @@ static struct msm_bus_vectors mdp_1080p_
},
};
+static struct msm_bus_vectors mdp_max_vectors[] = {
+ /* max */
+ {
+ .src = MSM_BUS_MASTER_MDP_PORT0,
+ .dst = MSM_BUS_SLAVE_EBI_CH0,
+ .ab = 2000000000,
+ .ib = 2000000000,
+ },
+};
+
static struct msm_bus_paths mdp_bus_scale_usecases[] = {
{
ARRAY_SIZE(mdp_init_vectors),
@@ -1467,6 +1477,10 @@ static struct msm_bus_paths mdp_bus_scal
ARRAY_SIZE(mdp_1080p_vectors),
mdp_1080p_vectors,
},
+ {
+ ARRAY_SIZE(mdp_max_vectors),
+ mdp_max_vectors,
+ },
};
static struct msm_bus_scale_pdata mdp_bus_scale_pdata = {
--- a/block/deadline-iosched.c
+++ b/block/deadline-iosched.c
@@ -17,10 +17,10 @@
/*
* See Documentation/block/deadline-iosched.txt
*/
-static const int read_expire = HZ / 2; /* max time before a read is submitted. */
+static const int read_expire = HZ / 4; /* max time before a read is submitted. */
static const int write_expire = 5 * HZ; /* ditto for writes, these limits are SOFT! */
-static const int writes_starved = 2; /* max times reads can starve a write */
-static const int fifo_batch = 16; /* # of sequential requests treated as one
+static const int writes_starved = 4; /* max times reads can starve a write */
+static const int fifo_batch = 1; /* # of sequential requests treated as one
by the above parameters. For throughput. */
struct deadline_data {
@@ -352,7 +352,7 @@ static void *deadline_init_queue(struct
dd->fifo_expire[READ] = read_expire;
dd->fifo_expire[WRITE] = write_expire;
dd->writes_starved = writes_starved;
- dd->front_merges = 1;
+ dd->front_merges = 0;
dd->fifo_batch = fifo_batch;
return dd;
}
--- a/drivers/video/msm/mdp4.h
+++ b/drivers/video/msm/mdp4.h
@@ -42,8 +42,7 @@ extern u32 mdp_max_clk;
#define CS_CONTROLLER_0 0x0707ffff
#define CS_CONTROLLER_1 0x03073f3f
-#if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_HD_PT)
-#define BLT_MODE_CHANGE_ISSUE
+#if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_HD_PT)
#define MDP4_ERROR
#endif
#if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_CMD_QHD_PT) \
@@ -58,7 +57,8 @@ enum {
OVERLAY_PERF_LEVEL1 = 1,
OVERLAY_PERF_LEVEL2,
OVERLAY_PERF_LEVEL3,
- OVERLAY_PERF_LEVEL4
+ OVERLAY_PERF_LEVEL4,
+ OVERLAY_PERF_LEVEL_MAX = 6,
};
enum mdp4_overlay_status {
@@ -587,9 +587,6 @@ void mdp4_dsi_video_fxn_register(cmd_fxn
void mdp4_dsi_video_overlay(struct msm_fb_data_type *mfd);
void mdp4_lcdc_vsync_ctrl(struct fb_info *info, int enable);
void mdp4_overlay0_done_dsi_video(int cndx);
-#ifdef BLT_MODE_CHANGE_ISSUE
-void mdp4_overlay0_done_blt_mode_change_recovery(int cndx);
-#endif
void mdp4_overlay0_done_dsi_cmd(int cndx);
void mdp4_primary_rdptr(void);
void mdp4_dsi_cmd_overlay(struct msm_fb_data_type *mfd);
--- a/drivers/video/msm/mdp4_overlay.c
+++ b/drivers/video/msm/mdp4_overlay.c
@@ -121,9 +121,6 @@ struct mdp4_overlay_perf perf_current =
static struct ion_client *display_iclient;
-#ifdef BLT_MODE_CHANGE_ISSUE
-extern int middle_of_blt_change;
-#endif
/*
* mdp4_overlay_iommu_unmap_freelist()
@@ -2908,12 +2905,6 @@ void mdp4_overlay_mdp_perf_upd(struct ms
{
struct mdp4_overlay_perf *perf_req = &perf_request;
struct mdp4_overlay_perf *perf_cur = &perf_current;
-#ifdef BLT_MODE_CHANGE_ISSUE /*Performance level upgrade temporarily*/
- bool blt_mode_perf_backup = false;
- u32 mdp_bw_backup = 0;
- u32 mdp_clk_backup = 0;
-#endif
-
pr_debug("%s %d: req mdp clk %d, cur mdp clk %d flag %d\n",
__func__, __LINE__,
@@ -2935,7 +2926,10 @@ void mdp4_overlay_mdp_perf_upd(struct ms
perf_cur->mdp_clk_rate =
perf_req->mdp_clk_rate;
}
- if (perf_req->mdp_bw < perf_cur->mdp_bw) {
+ if(perf_req->mdp_bw == OVERLAY_PERF_LEVEL_MAX) {
+ mdp_bus_scale_update_request(OVERLAY_PERF_LEVEL_MAX);
+ }
+ else if (perf_req->mdp_bw < perf_cur->mdp_bw) {
mdp_bus_scale_update_request
(OVERLAY_BUS_SCALE_TABLE_BASE -
perf_req->mdp_bw);
@@ -2952,35 +2946,7 @@ void mdp4_overlay_mdp_perf_upd(struct ms
mfd->panel_info.type == LVDS_PANEL)
mdp4_lcdc_overlay_blt_start(mfd);
else if (mfd->panel_info.type == MIPI_VIDEO_PANEL)
-#ifdef BLT_MODE_CHANGE_ISSUE
- {
- blt_mode_perf_backup = true;
- mdp_bw_backup = perf_request.mdp_bw;
- mdp_clk_backup = perf_request.mdp_clk_rate;
- perf_request.mdp_bw = OVERLAY_PERF_LEVEL1;
- perf_request.mdp_clk_rate = mdp_max_clk;
-
- mdp_set_core_clk(perf_request.mdp_clk_rate);
- mdp_bus_scale_update_request
- (OVERLAY_BUS_SCALE_TABLE_BASE -
- perf_request.mdp_bw);
-#endif
-
mdp4_dsi_video_blt_start(mfd);
-#ifdef BLT_MODE_CHANGE_ISSUE
- if(blt_mode_perf_backup == true)
- {
- blt_mode_perf_backup = false;
- perf_request.mdp_bw = mdp_bw_backup;
- perf_request.mdp_clk_rate = mdp_clk_backup;
-
- mdp_set_core_clk(perf_request.mdp_clk_rate);
- mdp_bus_scale_update_request
- (OVERLAY_BUS_SCALE_TABLE_BASE -
- perf_request.mdp_bw);
- }
- }
-#endif
else if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD)
mdp4_dsi_cmd_blt_start(mfd);
pr_info("%s mixer0 start blt [%d] from %d to %d.\n",
@@ -3011,7 +2977,7 @@ void mdp4_overlay_mdp_perf_upd(struct ms
perf_cur->mdp_clk_rate =
perf_req->mdp_clk_rate;
}
- if (perf_req->mdp_bw > perf_cur->mdp_bw) {
+ if (perf_req->mdp_bw > perf_cur->mdp_bw || perf_cur->mdp_bw == OVERLAY_PERF_LEVEL_MAX) {
pr_info("%s mdp bw is changed [%d] from %d to %d\n",
__func__,
flag,
@@ -3028,34 +2994,7 @@ void mdp4_overlay_mdp_perf_upd(struct ms
mfd->panel_info.type == LVDS_PANEL)
mdp4_lcdc_overlay_blt_stop(mfd);
else if (mfd->panel_info.type == MIPI_VIDEO_PANEL)
-#ifdef BLT_MODE_CHANGE_ISSUE
- {
- blt_mode_perf_backup = true;
- mdp_bw_backup = perf_request.mdp_bw;
- mdp_clk_backup = perf_request.mdp_clk_rate;
- perf_request.mdp_bw = OVERLAY_PERF_LEVEL1;
- perf_request.mdp_clk_rate = mdp_max_clk;
-
- mdp_set_core_clk(perf_request.mdp_clk_rate);
- mdp_bus_scale_update_request
- (OVERLAY_BUS_SCALE_TABLE_BASE -
- perf_request.mdp_bw);
-#endif
mdp4_dsi_video_blt_stop(mfd);
-#ifdef BLT_MODE_CHANGE_ISSUE
- if(blt_mode_perf_backup == true)
- {
- blt_mode_perf_backup = false;
- perf_request.mdp_bw = mdp_bw_backup;
- perf_request.mdp_clk_rate = mdp_clk_backup;
-
- mdp_set_core_clk(perf_request.mdp_clk_rate);
- mdp_bus_scale_update_request
- (OVERLAY_BUS_SCALE_TABLE_BASE -
- perf_request.mdp_bw);
- }
- }
-#endif
else if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD)
mdp4_dsi_cmd_blt_stop(mfd);
pr_info("%s mixer0 stop blt [%d] from %d to %d.\n",
--- a/drivers/video/msm/mdp4_overlay_dsi_video.c
+++ b/drivers/video/msm/mdp4_overlay_dsi_video.c
@@ -45,11 +45,9 @@ static int dsi_video_enabled;
#define MAX_CONTROLLER 1
-#ifdef BLT_MODE_CHANGE_ISSUE
-static struct wake_lock blt_mode_perf_up;
-static int blt_wake_lock_init = 0;
-extern int middle_of_blt_change;
-#endif
+extern struct mdp4_overlay_perf perf_request;
+static struct wake_lock blt_mode_perf_up;
+static int blt_wake_lock_init = 0;
static struct vsycn_ctrl {
struct device *dev;
@@ -163,6 +161,9 @@ int mdp4_dsi_video_pipe_commit(int cndx,
struct mdp4_overlay_pipe *real_pipe;
unsigned long flags;
int cnt = 0;
+ bool blt_mode_perf_backup = false;
+ u32 mdp_bw_backup = 0;
+ u32 mdp_clk_backup = 0;
vctrl = &vsync_ctrl_db[cndx];
@@ -199,9 +200,18 @@ int mdp4_dsi_video_pipe_commit(int cndx,
}
spin_unlock_irqrestore(&vctrl->spin_lock, flags);
+ if(vctrl->blt_change) {
+ blt_mode_perf_backup = true;
+ mdp_bw_backup = perf_request.mdp_bw;
+ mdp_clk_backup = perf_request.mdp_clk_rate;
+ perf_request.mdp_bw = OVERLAY_PERF_LEVEL_MAX;
+ perf_request.mdp_clk_rate = mdp_max_clk;
+ }
+
mdp4_overlay_mdp_perf_upd(vctrl->mfd, 1);
if (vctrl->blt_change) {
+ wake_lock(&blt_mode_perf_up);
pipe = vctrl->base_pipe;
spin_lock_irqsave(&vctrl->spin_lock, flags);
INIT_COMPLETION(vctrl->dmap_comp);
@@ -211,6 +221,11 @@ int mdp4_dsi_video_pipe_commit(int cndx,
mdp4_dsi_video_wait4dmap(0);
if (pipe->ov_blt_addr)
mdp4_dsi_video_wait4ov(0);
+ if(blt_mode_perf_backup == true){
+ perf_request.mdp_bw = mdp_bw_backup;
+ perf_request.mdp_clk_rate = mdp_clk_backup;
+ }
+ wake_unlock(&blt_mode_perf_up);
}
pipe = vp->plist;
@@ -689,13 +704,10 @@ int mdp4_dsi_video_on(struct platform_de
mdp_histogram_ctrl_all(TRUE);
-#ifdef BLT_MODE_CHANGE_ISSUE
- if(!blt_wake_lock_init)
- {
- wake_lock_init(&blt_mode_perf_up, WAKE_LOCK_IDLE, "blt_mode_wakelock");
- blt_wake_lock_init = true;
- }
-#endif
+ if(!blt_wake_lock_init) {
+ wake_lock_init(&blt_mode_perf_up, WAKE_LOCK_IDLE, "blt_mode_wakelock");
+ blt_wake_lock_init = true;
+ }
if (!vctrl->sysfs_created) {
ret = sysfs_create_group(&vctrl->dev->kobj,
@@ -984,26 +996,6 @@ void mdp4_dmap_done_dsi_video(int cndx)
spin_unlock(&vctrl->spin_lock);
}
-
-#ifdef BLT_MODE_CHANGE_ISSUE
-void mdp4_overlay0_done_blt_mode_change_recovery(int cndx)
-{
- struct vsycn_ctrl *vctrl;
- struct mdp4_overlay_pipe *pipe;
-
- vctrl = &vsync_ctrl_db[cndx];
- pipe = vctrl->base_pipe;
-
- spin_lock(&vctrl->spin_lock);
- vsync_irq_disable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);
- vctrl->ov_done++;
- complete_all(&vctrl->ov_comp);
- spin_unlock(&vctrl->spin_lock);
-
- return;
-}
-#endif
-
/*
* mdp4_overlay0_done_dsi: called from isr
*/
@@ -1039,9 +1031,7 @@ static void mdp4_dsi_video_do_blt(struct
int cndx = 0;
struct vsycn_ctrl *vctrl;
struct mdp4_overlay_pipe *pipe;
-#ifdef BLT_MODE_CHANGE_ISSUE
- int tg_enabled;
-#endif
+
vctrl = &vsync_ctrl_db[cndx];
pipe = vctrl->base_pipe;
@@ -1051,9 +1041,7 @@ static void mdp4_dsi_video_do_blt(struct
pr_info("%s: no blt_base assigned\n", __func__);
return;
}
-#ifdef BLT_MODE_CHANGE_ISSUE
- wake_lock(&blt_mode_perf_up);
-#endif
+
spin_lock_irqsave(&vctrl->spin_lock, flag);
if (enable && pipe->ov_blt_addr == 0) {
pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr;
@@ -1077,27 +1065,10 @@ static void mdp4_dsi_video_do_blt(struct
if (!vctrl->blt_change) {
spin_unlock_irqrestore(&vctrl->spin_lock, flag);
-#ifdef BLT_MODE_CHANGE_ISSUE
- wake_unlock(&blt_mode_perf_up);
-#endif
return;
}
spin_unlock_irqrestore(&vctrl->spin_lock, flag);
- #ifdef BLT_MODE_CHANGE_ISSUE
- tg_enabled = inpdw(MDP_BASE + DSI_VIDEO_BASE) & 0x01;
- if(middle_of_blt_change != 3)
- middle_of_blt_change = TRUE;
- if (tg_enabled) {
- mdp4_dsi_video_wait4dmap_done(0);
- if (pipe->ov_blt_addr)
- mdp4_dsi_video_wait4ov(0);
- vctrl->blt_change = 0;
- }
- vctrl->blt_change = 0;
- middle_of_blt_change = FALSE;
- wake_unlock(&blt_mode_perf_up);
-#endif
}
void mdp4_dsi_video_overlay_blt(struct msm_fb_data_type *mfd,
@@ -1154,7 +1125,7 @@ void mdp4_dsi_video_overlay(struct msm_f
int ret = mdp4_dsi_video_pipe_commit(0, 0);
mutex_unlock(&mfd->dma->ov_mutex);
-
+
if (ret) {
if (pipe->ov_blt_addr)
mdp4_dsi_video_wait4ov(0);
--- a/drivers/video/msm/mdp4_util.c
+++ b/drivers/video/msm/mdp4_util.c
@@ -33,10 +33,6 @@
#include "msm_fb.h"
#include "mdp4.h"
-#ifdef BLT_MODE_CHANGE_ISSUE
-int middle_of_blt_change = 0;
-#endif
-
struct mdp4_statistic mdp4_stat;
unsigned is_mdp4_hw_reset(void)
@@ -400,14 +396,6 @@ irqreturn_t mdp4_isr(int irq, void *ptr)
if (isr & INTR_PRIMARY_INTF_UDERRUN) {
pr_debug("%s: UNDERRUN -- primary\n", __func__);
mdp4_stat.intr_underrun_p++;
-#ifdef BLT_MODE_CHANGE_ISSUE
- if(middle_of_blt_change)
- {
- mdp4_overlay0_done_blt_mode_change_recovery(0);
- middle_of_blt_change = 3;
- }
-#endif
-
#ifdef MDP_HANG_DEBUG
pr_info("-=-=-=-=-=-=-=-=-=- UNDER RUN -=-=-=\n");
mdp4_dump_regs();
--- a/drivers/video/msm/mipi_samsung_oled.c
+++ b/drivers/video/msm/mipi_samsung_oled.c
@@ -1034,7 +1034,8 @@ static void mipi_samsung_disp_late_resum
{
struct msm_fb_data_type *mfd;
#if defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_CMD_QHD_PT) \
- || defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_WVGA_PT)
+ || defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_WVGA_PT) \
+ || defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_VIDEO_HD_PT)
is_negativeMode_on();
#endif
mfd = platform_get_drvdata(msd.msm_pdev);
projects / ziggy471-sgs3-jb.git / commitdiff