--- a/arch/arm/mach-msm/acpuclock-8960.c

+++ b/arch/arm/mach-msm/acpuclock-8960.c

@@ -1290,8 +1290,8 @@ static const int krait_needs_vmin(void)

static void kraitv2_apply_vmin(struct acpu_level *tbl)

{

for (; tbl->speed.khz != 0; tbl++)

- if (tbl->vdd_core < 1150000)

- tbl->vdd_core = 1150000;

+ if (tbl->vdd_core < CONFIG_MSM_VMIN)

+ tbl->vdd_core = CONFIG_MSM_VMIN;

}

#ifdef CONFIG_SEC_L1_DCACHE_PANIC_CHK

--- a/drivers/cpufreq/Kconfig

+++ b/drivers/cpufreq/Kconfig

@@ -17,6 +17,8 @@ config CPU_FREQ

if CPU_FREQ

+if ARCH_MSM

+

config CPU_FREQ_MIN_SCALING_LIMIT

int "Min CPU Scaling Frequency Limit"

depends on CPU_FREQ

@@ -27,6 +29,11 @@ config CPU_FREQ_MAX_SCALING_LIMIT

depends on CPU_FREQ

default 1900000

+config MSM_VMIN

+ int "VMIN used for acpuclock"

+ default 900000

+ depends on CPU_FREQ

+

config CPU_FREQ_MAX_VDD_SC

int "Max CPU VDD SC uV"

depends on CPU_FREQ

@@ -45,7 +52,9 @@ config CPU_FREQ_MSM_DCVS_CPU1_DELAY

The MSM-DCVS governor sometimes does not register

the second cpu, cpu1, correctly. This delay gives

cpu1 additional time to become ready prior to registering

-

+

+endif

+

config CPU_FREQ_TABLE

tristate