--- a/arch/arm/mach-msm/acpuclock-8960.c
+++ b/arch/arm/mach-msm/acpuclock-8960.c
@@ -71,7 +71,7 @@
#define STBY_KHZ 1
#define HFPLL_NOMINAL_VDD 1050000
-#define HFPLL_LOW_VDD 850000
+#define HFPLL_LOW_VDD 800000
#define HFPLL_LOW_VDD_PLL_L_MAX 0x28
#define SECCLKAGD BIT(4)
@@ -143,7 +143,7 @@ static struct scalable scalable_8960[] =
.hfpll_base = MSM_HFPLL_BASE + 0x200,
.aux_clk_sel = MSM_ACC0_BASE + 0x014,
.l2cpmr_iaddr = L2CPUCPMR_IADDR,
- .vreg[VREG_CORE] = { "krait0", 1300000 },
+ .vreg[VREG_CORE] = { "krait0", 1350000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000,
RPM_VREG_VOTER1,
RPM_VREG_ID_PM8921_L24 },
@@ -161,7 +161,7 @@ static struct scalable scalable_8960[] =
.hfpll_base = MSM_HFPLL_BASE + 0x300,
.aux_clk_sel = MSM_ACC1_BASE + 0x014,
.l2cpmr_iaddr = L2CPUCPMR_IADDR,
- .vreg[VREG_CORE] = { "krait1", 1300000 },
+ .vreg[VREG_CORE] = { "krait1", 1350000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000,
RPM_VREG_VOTER2,
RPM_VREG_ID_PM8921_L24 },
@@ -382,6 +382,7 @@ static struct msm_bus_paths bw_level_tbl
[4] = BW_MBPS(3200), /* At least 400 MHz on bus. */
[5] = BW_MBPS(3600), /* At least 450 MHz on bus. */
[6] = BW_MBPS(3936), /* At least 492 MHz on bus. */
+ [7] = BW_MBPS(4264), /* At least 533 MHz on bus. */
};
static struct msm_bus_scale_pdata bus_client_pdata = {
@@ -685,10 +686,10 @@ static struct l2_level l2_freq_tbl_8960_
[13] = { { 1026000, HFPLL, 1, 0, 0x26 }, 1150000, 1150000, 6 },
[14] = { { 1080000, HFPLL, 1, 0, 0x28 }, 1150000, 1150000, 6 },
[15] = { { 1134000, HFPLL, 1, 0, 0x2A }, 1150000, 1150000, 6 },
- [16] = { { 1188000, HFPLL, 1, 0, 0x2C }, 1150000, 1150000, 6 },
- [17] = { { 1242000, HFPLL, 1, 0, 0x2E }, 1150000, 1150000, 6 },
- [18] = { { 1296000, HFPLL, 1, 0, 0x30 }, 1150000, 1150000, 6 },
- [19] = { { 1350000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 6 },
+ [16] = { { 1188000, HFPLL, 1, 0, 0x2C }, 1150000, 1150000, 7 },
+ [17] = { { 1242000, HFPLL, 1, 0, 0x2E }, 1150000, 1150000, 7 },
+ [18] = { { 1296000, HFPLL, 1, 0, 0x30 }, 1150000, 1150000, 7 },
+ [19] = { { 1350000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 7 },
};
static struct acpu_level acpu_freq_tbl_8960_kraitv2_slow[] = {
@@ -719,37 +720,41 @@ static struct acpu_level acpu_freq_tbl_8
};
static struct acpu_level acpu_freq_tbl_8960_kraitv2_nom[] = {
- { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 900000 },
- { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 900000 },
- { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 925000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 925000 },
- { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 950000 },
- { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(7), 950000 },
- { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(7), 975000 },
- { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 975000 },
- { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(7), 1025000 },
- { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(7), 1025000 },
- { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(7), 1050000 },
- { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(7), 1050000 },
- { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(7), 1075000 },
- { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(7), 1075000 },
- { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(16), 1125000 },
- { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(16), 1125000 },
- { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1150000 },
- { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1150000 },
- { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1175000 },
- { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1175000 },
- { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1187500 },
- { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(16), 1187500 },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(16), 1200000 },
+ { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 800000 },
+ { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 800000 },
+ { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 825000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 850000 },
+ { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 850000 },
+ { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(7), 850000 },
+ { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(7), 900000 },
+ { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 900000 },
+ { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(7), 950000 },
+ { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(7), 950000 },
+ { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(7), 975000 },
+ { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(7), 975000 },
+ { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(7), 1025000 },
+ { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(7), 1025000 },
+ { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(16), 1050000 },
+ { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(16), 1050000 },
+ { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1075000 },
+ { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1075000 },
+ { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1125000 },
+ { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1125000 },
+ { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1125000 },
+ { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(16), 1150000 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(18), 1150000 },
+ { 1, { 1674000, HFPLL, 1, 0, 0x3A }, L2(18), 1200000 },
+ { 1, { 1728000, HFPLL, 1, 0, 0x3C }, L2(19), 1200000 },
+ { 1, { 1809000, HFPLL, 1, 0, 0x3E }, L2(19), 1250000 },
+ { 1, { 1900000, HFPLL, 1, 0, 0x40 }, L2(19), 1300000 },
{ 0, { 0 } }
};
static struct acpu_level acpu_freq_tbl_8960_kraitv2_fast[] = {
{ 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 850000 },
{ 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 850000 },
- { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 875000 },
- { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 875000 },
+ { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 850000 },
+ { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 850000 },
{ 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 900000 },
{ 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(7), 900000 },
{ 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(7), 925000 },
@@ -766,9 +771,13 @@ static struct acpu_level acpu_freq_tbl_8
{ 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(16), 1100000 },
{ 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(16), 1125000 },
{ 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(16), 1125000 },
- { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1137500 },
+ { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(16), 1125000 },
{ 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(16), 1137500 },
- { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(16), 1150000 },
+ { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(18), 1150000 },
+ { 1, { 1674000, HFPLL, 1, 0, 0x3A }, L2(18), 1175000 },
+ { 1, { 1728000, HFPLL, 1, 0, 0x3C }, L2(19), 1200000 },
+ { 1, { 1809000, HFPLL, 1, 0, 0x3E }, L2(19), 1250000 },
+ { 1, { 1998000, HFPLL, 1, 0, 0x42 }, L2(19), 1300000 },
{ 0, { 0 } }
};
@@ -1474,7 +1483,7 @@ static void __init bus_init(unsigned int
}
#ifdef CONFIG_CPU_FREQ_MSM
-static struct cpufreq_frequency_table freq_table[NR_CPUS][30];
+static struct cpufreq_frequency_table freq_table[NR_CPUS][34];
static void __init cpufreq_table_init(void)
{
@@ -1599,24 +1608,12 @@ static struct acpu_level * __init select
switch (pvs) {
case 0x0:
case 0x7:
- pr_alert("ACPU PVS: Slow\n");
- v1 = acpu_freq_tbl_8960_kraitv1_slow;
- v2 = acpu_freq_tbl_8960_kraitv2_slow;
- break;
case 0x1:
- pr_alert("ACPU PVS: Nominal\n");
- v1 = acpu_freq_tbl_8960_kraitv1_nom_fast;
- v2 = acpu_freq_tbl_8960_kraitv2_nom;
- break;
case 0x3:
+ default:
pr_alert("ACPU PVS: Fast\n");
v1 = acpu_freq_tbl_8960_kraitv1_nom_fast;
- v2 = acpu_freq_tbl_8960_kraitv2_fast;
- break;
- default:
- pr_err("ACPU PVS: Unknown. Defaulting to slow.\n");
- v1 = acpu_freq_tbl_8960_kraitv1_slow;
- v2 = acpu_freq_tbl_8960_kraitv2_slow;
+ v2 = acpu_freq_tbl_8960_kraitv2_nom;
break;
}
@@ -1652,9 +1649,11 @@ static struct acpu_level * __init select
kraitv2_apply_vmin(acpu_freq_tbl);
/* Find the max supported scaling frequency. */
- for (l = acpu_freq_tbl; l->speed.khz != 0; l++)
+ for (l = acpu_freq_tbl; l->speed.khz != 0; l++) {
if (l->use_for_scaling)
max_acpu_level = l;
+ if (l->speed.khz > 1458000) break;
+ }
BUG_ON(!max_acpu_level);
pr_info("Max ACPU freq: %u KHz\n", max_acpu_level->speed.khz);
--- a/arch/arm/mach-msm/board-8960-regulator.c
+++ b/arch/arm/mach-msm/board-8960-regulator.c
@@ -524,9 +524,9 @@ struct gpio_regulator_platform_data msm_
/* SAW regulator constraints */
struct regulator_init_data msm_saw_regulator_pdata_s5 =
/* ID vreg_name min_uV max_uV */
- SAW_VREG_INIT(S5, "8921_s5", 850000, 1300000);
+ SAW_VREG_INIT(S5, "8921_s5", 800000, 1350000);
struct regulator_init_data msm_saw_regulator_pdata_s6 =
- SAW_VREG_INIT(S6, "8921_s6", 850000, 1300000);
+ SAW_VREG_INIT(S6, "8921_s6", 800000, 1350000);
/* PM8921 regulator constraints */
struct pm8xxx_regulator_platform_data
--- a/drivers/cpufreq/cpufreq.c
+++ b/drivers/cpufreq/cpufreq.c
@@ -1116,6 +1116,9 @@ static int cpufreq_add_dev(struct sys_de
pr_debug("initialization failed\n");
goto err_unlock_policy;
}
+
+ if (policy->max > 1512000) policy->max = 1512000;
+
policy->user_policy.min = policy->min;
policy->user_policy.max = policy->max;
--- a/drivers/thermal/msm_thermal.c
+++ b/drivers/thermal/msm_thermal.c
@@ -47,6 +47,7 @@ static int update_cpu_max_freq(struct cp
cpufreq_verify_within_limits(cpu_policy,
cpu_policy->min, max_freq);
+ if (max_freq > 1512000) max_freq = 1512000;
cpu_policy->user_policy.max = max_freq;
ret = cpufreq_update_policy(cpu);
@@ -93,9 +94,8 @@ static void check_temp(struct work_struc
} else if (temp < allowed_max_low) {
#ifdef CONFIG_SEC_DVFS
if (cpufreq_get_dvfs_state() != 1) {
- if (cpu_policy->max
- < cpu_policy->cpuinfo.max_freq) {
- max_freq = cpu_policy->cpuinfo.max_freq;
+ if (cpu_policy->max < 1512000) {
+ max_freq = 1512000;
update_policy = 1;
}
} else
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -353,7 +353,7 @@ static inline unsigned int cpufreq_quick
#define LOW_MAX_FREQ_LIMIT 1188000
#define MIN_FREQ_LIMIT 384000
-#define MAX_FREQ_LIMIT 1512000
+#define MAX_FREQ_LIMIT 1900000
enum {
SET_MIN = 0,
projects / ziggy471-i535-kernel.git / commitdiff