--- 16a86dd1c827787cd5454d4de871f612334c6697
+++ e4fcb7b759ca286a565c04784764e34bacc1754f
@@ -70,7 +70,6 @@
 
 #define MAX_VDD_SC		CONFIG_CPU_FREQ_MAX_VDD_SC /* uV */
 #define MIN_VDD_SC		CONFIG_CPU_FREQ_MIN_VDD_SC /* uV */
-int VMIN = CONFIG_MSM_VMIN;
 
 #define HFPLL_NOMINAL_VDD	1050000
 #define HFPLL_LOW_VDD		CONFIG_CPU_FREQ_MIN_VDD_SC
@@ -130,7 +129,6 @@ struct acpu_level {
 	struct core_speed	speed;
 	struct l2_level		*l2_level;
 	unsigned int		vdd_core;
-	unsigned int		vdd_core_save;
 };
 
 struct scalable {
@@ -478,10 +476,10 @@ static struct acpu_level acpu_freq_tbl_8
 	{ 1, {   702000, HFPLL, 1, 0, 0x1A }, L2(7),   900000 },
 	{ 0, {   756000, HFPLL, 1, 0, 0x1C }, L2(8),   950000 },
 	{ 1, {   810000, HFPLL, 1, 0, 0x1E }, L2(9),   950000 },
-	{ 0, {   864000, HFPLL, 1, 0, 0x20 }, L2(10),  975000 },
-	{ 1, {   918000, HFPLL, 1, 0, 0x22 }, L2(11),  975000 },
-	{ 0, {   972000, HFPLL, 1, 0, 0x24 }, L2(12), 1025000 },
-	{ 1, {  1026000, HFPLL, 1, 0, 0x26 }, L2(13), 1025000 },
+	{ 0, {   864000, HFPLL, 1, 0, 0x20 }, L2(10),   975000 },
+	{ 1, {   918000, HFPLL, 1, 0, 0x22 }, L2(11),   975000 },
+	{ 0, {   972000, HFPLL, 1, 0, 0x24 }, L2(12),  1025000 },
+	{ 1, {  1026000, HFPLL, 1, 0, 0x26 }, L2(13),  1025000 },
 	{ 0, {  1080000, HFPLL, 1, 0, 0x28 }, L2(14), 1050000 },
 	{ 1, {  1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1050000 },
 	{ 0, {  1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1075000 },
@@ -1277,6 +1275,7 @@ static struct notifier_block __cpuinitda
 	.notifier_call = acpuclock_cpu_callback,
 };
 
+#if 0
 static const int krait_needs_vmin(void)
 {
 	switch (read_cpuid_id()) {
@@ -1291,14 +1290,11 @@ static const int krait_needs_vmin(void)
 
 static void kraitv2_apply_vmin(struct acpu_level *tbl)
 {
-	for (; tbl->speed.khz != 0; tbl++) {
-		tbl->vdd_core_save = tbl->vdd_core;
-		if (tbl->vdd_core < VMIN) {
-			pr_info("%8u: cur-vdd %4d - new-vdd %4d", tbl->speed.khz, tbl->vdd_core, VMIN);
-			tbl->vdd_core = VMIN;
-		}
-	}
+	for (; tbl->speed.khz != 0; tbl++)
+		if (tbl->vdd_core < MIN_VDD_SC)
+			tbl->vdd_core = MIN_VDD_SC;
 }
+#endif
 
 #ifdef CONFIG_SEC_L1_DCACHE_PANIC_CHK
 uint32_t global_sec_pvs_value;
@@ -1397,18 +1393,19 @@ static struct acpu_level * __init select
 	} else {
 		BUG();
 	}
+#if 0
 	if (krait_needs_vmin())
 		kraitv2_apply_vmin(acpu_freq_tbl);
+#endif
 
 	/* Find the max supported scaling frequency. */
-	for (l = acpu_freq_tbl; l->speed.khz != 0; l++) {
-		if (l->use_for_scaling) {
+	for (l = acpu_freq_tbl; l->speed.khz != 0; l++)
+		if (l->use_for_scaling)
 			if (l->speed.khz <= MAX_FREQ_LIMIT)
 				max_acpu_level = l;
 			else
 				l->use_for_scaling = 0;
-		}
-	}
+				
 	BUG_ON(!max_acpu_level);
 	pr_info("Max ACPU freq: %u KHz\n", max_acpu_level->speed.khz);
 
@@ -1474,18 +1471,4 @@ void acpuclk_set_vdd(unsigned int khz, i
 	}
 	mutex_unlock(&driver_lock);
 }
-
-void acpuclk_set_vmin(int newvmin)
-{
-	int i;
-
-	if (krait_needs_vmin()) {
-		if (newvmin >= MIN_VDD_SC && newvmin <= MAX_VDD_SC) {
-			VMIN = newvmin;
-			for (i = 0; acpu_freq_tbl[i].speed.khz; i++)
-				acpu_freq_tbl[i].vdd_core = acpu_freq_tbl[i].vdd_core_save;
-			kraitv2_apply_vmin(acpu_freq_tbl);
-		}
-	}
-}
 #endif