--- a6eb8666c88765858c0293e8c56d9cef9ae6302c
+++ d0b2bd53c0a0f74eeb8b6f79971aafeb8cf7b1c7
@@ -397,7 +397,6 @@ static struct msm_bus_paths bw_level_tbl
 	[7] = BW_MBPS(4264), /* At least 533 MHz on bus. */
 	[8] = BW_MBPS(4532), /* At least 566 MHz on bus. */
 	[9] = BW_MBPS(4624), /* At least 578 MHz on bus. */
-	[10] = BW_MBPS(4800), /* At least 600 MHz on bus. */
 };
 
 static struct msm_bus_scale_pdata bus_client_pdata = {
@@ -464,8 +463,8 @@ static struct acpu_level acpu_freq_tbl_8
 
 static struct l2_level l2_freq_tbl_8960_kraitv2[] = {
 	[0]  = { {STBY_KHZ, QSB,   0, 0, 0x00 }, 1050000, 1050000, 0 },
-	[1]  = { {  384000, PLL_8, 0, 2, 0x00 }, 1050000, 1050000, 1 }, //133mhz fsb
-	[2]  = { {  432000, HFPLL, 2, 0, 0x20 }, 1050000, 1050000, 3 }, //266mhz fsb
+	[1]  = { {  192000, PLL_8, 0, 2, 0x00 }, 1050000, 1050000, 1 }, //133mhz fsb
+	[2]  = { {  384000, HFPLL, 2, 0, 0x20 }, 1050000, 1050000, 3 }, //266mhz fsb
 	[3]  = { {  486000, HFPLL, 2, 0, 0x24 }, 1050000, 1050000, 3 }, //266mhz fsb 
 	[4]  = { {  540000, HFPLL, 2, 0, 0x28 }, 1050000, 1050000, 3 }, //266mhz fsb
 	[5]  = { {  594000, HFPLL, 1, 0, 0x16 }, 1050000, 1050000, 3 }, //266mhz fsb
@@ -483,10 +482,10 @@ static struct l2_level l2_freq_tbl_8960_
 	[17] = { { 1242000, HFPLL, 1, 0, 0x2E }, 1150000, 1150000, 7 }, //533mhz fsb
 	[18] = { { 1296000, HFPLL, 1, 0, 0x30 }, 1150000, 1150000, 7 }, //533mhz fsb
 	[19] = { { 1350000, HFPLL, 1, 0, 0x31 }, 1150000, 1150000, 7 }, //533mhz fsb
-	[20] = { { 1458000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 8 }, //533mhz fsb
+	[20] = { { 1458000, HFPLL, 1, 0, 0x32 }, 1150000, 1150000, 7 }, //533mhz fsb
 	[21] = { { 1512000, HFPLL, 1, 0, 0x33 }, 1150000, 1150000, 8 }, //566mhz fsb
-	[22] = { { 1674000, HFPLL, 1, 0, 0x34 }, 1150000, 1150000, 9 }, //578mhz fsb
-	[23] = { { 1728000, HFPLL, 1, 0, 0x35 }, 1150000, 1150000, 10 }, //600mhz fsb
+	[22] = { { 1674000, HFPLL, 1, 0, 0x34 }, 1150000, 1150000, 8 }, //566mhz fsb
+	
 };
 
 static struct acpu_level acpu_freq_tbl_8960_kraitv2_slow[] = {
@@ -514,11 +513,9 @@ static struct acpu_level acpu_freq_tbl_8
 	{ 1, {  1458000, HFPLL, 1, 0, 0x36 }, L2(20), 1237500 },
 	{ 1, {  1512000, HFPLL, 1, 0, 0x38 }, L2(21), 1250000 },
 	{ 1, {  1674000, HFPLL, 1, 0, 0x3A }, L2(22), 1250000 },
-	{ 1, {  1728000, HFPLL, 1, 0, 0x3C }, L2(23), 1262500 },
-	{ 1, {  1809000, HFPLL, 1, 0, 0x3E }, L2(21), 1262500 },
-	{ 1, {  1890000, HFPLL, 1, 0, 0x40 }, L2(21), 1300000 },
-	{ 1, {  1998000, HFPLL, 1, 0, 0x42 }, L2(20), 1325000 },
-	{ 1, {  2106000, HFPLL, 1, 0, 0x44 }, L2(20), 1350000 },
+	{ 1, {  1728000, HFPLL, 1, 0, 0x3C }, L2(22), 1262500 },
+	{ 1, {  1809000, HFPLL, 1, 0, 0x3E }, L2(22), 1262500 },
+	{ 1, {  1890000, HFPLL, 1, 0, 0x40 }, L2(22), 1300000 },
 	{ 0, { 0 } }
 };
 
@@ -547,11 +544,9 @@ static struct acpu_level acpu_freq_tbl_8
 	{ 1, {  1458000, HFPLL, 1, 0, 0x36 }, L2(20), 1187500 },
 	{ 1, {  1512000, HFPLL, 1, 0, 0x38 }, L2(21), 1200000 },
 	{ 1, {  1674000, HFPLL, 1, 0, 0x3A }, L2(22), 1200000 },
-	{ 1, {  1728000, HFPLL, 1, 0, 0x3C }, L2(23), 1250000 },
-	{ 1, {  1809000, HFPLL, 1, 0, 0x3E }, L2(21), 1275000 },
-	{ 1, {  1900000, HFPLL, 1, 0, 0x40 }, L2(21), 1300000 },
-	{ 1, {  1998000, HFPLL, 1, 0, 0x42 }, L2(20), 1325000 },
-	{ 1, {  2106000, HFPLL, 1, 0, 0x44 }, L2(20), 1350000 },
+	{ 1, {  1728000, HFPLL, 1, 0, 0x3C }, L2(22), 1250000 },
+	{ 1, {  1809000, HFPLL, 1, 0, 0x3E }, L2(22), 1275000 },
+	{ 1, {  1900000, HFPLL, 1, 0, 0x40 }, L2(22), 1300000 },
 	{ 0, { 0 } }
 };
 
@@ -580,11 +575,9 @@ static struct acpu_level acpu_freq_tbl_8
 	{ 1, {  1458000, HFPLL, 1, 0, 0x36 }, L2(20), 1137500 },
 	{ 1, {  1512000, HFPLL, 1, 0, 0x38 }, L2(21), 1150000 },
 	{ 1, {  1674000, HFPLL, 1, 0, 0x3A }, L2(22), 1175000 },
-	{ 1, {  1728000, HFPLL, 1, 0, 0x3C }, L2(23), 1200000 },
-	{ 1, {  1809000, HFPLL, 1, 0, 0x3E }, L2(21), 1250000 },
-	{ 1, {  1900000, HFPLL, 1, 0, 0x40 }, L2(21), 1300000 },
-	{ 1, {  1998000, HFPLL, 1, 0, 0x42 }, L2(20), 1325000 },
-	{ 1, {  2106000, HFPLL, 1, 0, 0x44 }, L2(20), 1350000 },
+	{ 1, {  1728000, HFPLL, 1, 0, 0x3C }, L2(22), 1200000 },
+	{ 1, {  1809000, HFPLL, 1, 0, 0x3E }, L2(22), 1250000 },
+	{ 1, {  1900000, HFPLL, 1, 0, 0x40 }, L2(22), 1300000 },
 	{ 0, { 0 } }
 };
 
@@ -613,11 +606,9 @@ static struct acpu_level acpu_freq_tbl_8
 	{ 1, {  1458000, HFPLL, 1, 0, 0x36 }, L2(20), 1112500 },
 	{ 1, {  1512000, HFPLL, 1, 0, 0x38 }, L2(21), 1125000 },
 	{ 1, {  1674000, HFPLL, 1, 0, 0x3A }, L2(22), 1175000 },
-	{ 1, {  1728000, HFPLL, 1, 0, 0x3C }, L2(23), 1200000 },
-	{ 1, {  1809000, HFPLL, 1, 0, 0x3E }, L2(21), 1250000 },
-	{ 1, {  1900000, HFPLL, 1, 0, 0x40 }, L2(21), 1300000 },
-	{ 1, {  1998000, HFPLL, 1, 0, 0x42 }, L2(20), 1325000 },
-	{ 1, {  2106000, HFPLL, 1, 0, 0x44 }, L2(20), 1350000 },
+	{ 1, {  1728000, HFPLL, 1, 0, 0x3C }, L2(22), 1200000 },
+	{ 1, {  1809000, HFPLL, 1, 0, 0x3E }, L2(22), 1250000 },
+	{ 1, {  1900000, HFPLL, 1, 0, 0x40 }, L2(22), 1300000 },
 	{ 0, { 0 } }
 };
 
@@ -1231,7 +1222,7 @@ static void __init hfpll_init(struct sca
 }
 
 /* Voltage regulator initialization. */
-static void regulator_init(int set_vdd)
+static void __init regulator_init(int set_vdd)
 {
 	int cpu, ret;
 	struct scalable *sc;
@@ -1262,7 +1253,7 @@ static void regulator_init(int set_vdd)
 }
 
 /* Set initial rate for a given core. */
-static void init_clock_sources(struct scalable *sc,
+static void __init init_clock_sources(struct scalable *sc,
 				      struct core_speed *tgt_s)
 {
 	uint32_t regval;
@@ -1292,7 +1283,7 @@ static void init_clock_sources(struct sc
 	sc->first_set_call = true;
 }
 
-static void per_cpu_init(void *data)
+static void __init per_cpu_init(void *data)
 {
 	struct acpu_level *max_acpu_level = data;
 	int cpu = smp_processor_id();
@@ -1318,9 +1309,9 @@ static void __init bus_init(unsigned int
 }
 
 #ifdef CONFIG_CPU_FREQ_MSM
-static struct cpufreq_frequency_table freq_table[NR_CPUS][FREQ_TABLE_SIZE];
+static struct cpufreq_frequency_table freq_table[NR_CPUS][34];
 
-static void cpufreq_table_init(void)
+static void __init cpufreq_table_init(void)
 {
 	int cpu;