--- 7eeb3bbedf0a2b234902c0ca50e30465add2efa5 +++ 16a86dd1c827787cd5454d4de871f612334c6697 @@ -68,17 +68,13 @@ #define STBY_KHZ 1 -#define MAX_VDD_SC 1400000 /* uV */ -#define MIN_VDD_SC 700000 /* uV */ +#define MAX_VDD_SC CONFIG_CPU_FREQ_MAX_VDD_SC /* uV */ +#define MIN_VDD_SC CONFIG_CPU_FREQ_MIN_VDD_SC /* uV */ +int VMIN = CONFIG_MSM_VMIN; -#ifdef CONFIG_VDD_USERSPACE -#define HFPLL_NOMINAL_VDD 1050000 -#define HFPLL_LOW_VDD 700000 -#else #define HFPLL_NOMINAL_VDD 1050000 -#define HFPLL_LOW_VDD 850000 -#endif -#define HFPLL_HIGH_VDD 1400000 +#define HFPLL_LOW_VDD CONFIG_CPU_FREQ_MIN_VDD_SC +#define HFPLL_HIGH_VDD CONFIG_CPU_FREQ_MAX_VDD_SC #define HFPLL_LOW_VDD_PLL_L_MAX 0x28 #define SECCLKAGD BIT(4) @@ -134,6 +130,7 @@ struct acpu_level { struct core_speed speed; struct l2_level *l2_level; unsigned int vdd_core; + unsigned int vdd_core_save; }; struct scalable { @@ -151,11 +148,11 @@ static struct scalable scalable_8960[] = .hfpll_base = MSM_HFPLL_BASE + 0x200, .aux_clk_sel = MSM_ACC0_BASE + 0x014, .l2cpmr_iaddr = L2CPUCPMR_IADDR, - .vreg[VREG_CORE] = { "krait0", 1400000 }, - .vreg[VREG_MEM] = { "krait0_mem", 1250000, + .vreg[VREG_CORE] = { "krait0", CONFIG_CPU_FREQ_MAX_VDD_SC }, + .vreg[VREG_MEM] = { "krait0_mem", 1150000, RPM_VREG_VOTER1, RPM_VREG_ID_PM8921_L24 }, - .vreg[VREG_DIG] = { "krait0_dig", 1250000, + .vreg[VREG_DIG] = { "krait0_dig", 1150000, RPM_VREG_VOTER1, RPM_VREG_ID_PM8921_S3 }, .vreg[VREG_HFPLL_A] = { "hfpll", 2100000, @@ -169,11 +166,11 @@ static struct scalable scalable_8960[] = .hfpll_base = MSM_HFPLL_BASE + 0x300, .aux_clk_sel = MSM_ACC1_BASE + 0x014, .l2cpmr_iaddr = L2CPUCPMR_IADDR, - .vreg[VREG_CORE] = { "krait1", 1400000 }, - .vreg[VREG_MEM] = { "krait0_mem", 1250000, + .vreg[VREG_CORE] = { "krait1", CONFIG_CPU_FREQ_MAX_VDD_SC }, + .vreg[VREG_MEM] = { "krait0_mem", 1150000, RPM_VREG_VOTER2, RPM_VREG_ID_PM8921_L24 }, - .vreg[VREG_DIG] = { "krait0_dig", 1250000, + .vreg[VREG_DIG] = { "krait0_dig", 1150000, RPM_VREG_VOTER2, RPM_VREG_ID_PM8921_S3 }, .vreg[VREG_HFPLL_A] = { "hfpll", 2100000, @@ -424,34 +421,18 @@ static struct l2_level l2_freq_tbl_8960_ [11] = { { 918000, HFPLL, 1, 0, 0x22 }, 1150000, 1150000, 3 }, }; -static struct acpu_level acpu_freq_tbl_8960_kraitv1_slow[] = { - { 0, {STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 900000 }, - { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 900000 }, - { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(2), 925000 }, - { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(3), 925000 }, - { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(4), 937500 }, - { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(5), 962500 }, - { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 987500 }, - { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 1000000 }, - { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(8), 1025000 }, - { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(9), 1062500 }, - { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(10), 1062500 }, - { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(11), 1087500 }, - { 0, { 0 } } -}; - static struct acpu_level acpu_freq_tbl_8960_kraitv1_nom_fast[] = { { 0, {STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 862500 }, { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 862500 }, - { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(2), 862500 }, - { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(3), 887500 }, - { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(4), 900000 }, - { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(5), 925000 }, + { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(6), 862500 }, + { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(6), 887500 }, + { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(6), 900000 }, + { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(6), 925000 }, { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 925000 }, { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 937500 }, - { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(8), 962500 }, - { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(9), 1012500 }, - { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(10), 1025000 }, + { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(11), 962500 }, + { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(11), 1012500 }, + { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(11), 1025000 }, { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(11), 1025000 }, { 0, { 0 } } }; @@ -459,7 +440,6 @@ static struct acpu_level acpu_freq_tbl_8 #undef L2 #define L2(x) (&l2_freq_tbl_8960_kraitv2[(x)]) - static struct l2_level l2_freq_tbl_8960_kraitv2[] = { [0] = { {STBY_KHZ, QSB, 0, 0, 0x00 }, 1050000, 1050000, 0 }, [1] = { { 384000, PLL_8, 0, 2, 0x00 }, 1050000, 1050000, 1 }, //133mhz fsb @@ -487,135 +467,34 @@ static struct l2_level l2_freq_tbl_8960_ [23] = { { 1728000, HFPLL, 1, 0, 0x35 }, 1150000, 1150000, 11 }, //6667mhz fsb }; -static struct acpu_level acpu_freq_tbl_8960_kraitv2_slow[] = { - { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 950000 }, - { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 950000 }, - { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(2), 975000 }, - { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(3), 975000 }, - { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(4), 1000000 }, - { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(5), 1000000 }, - { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 1025000 }, - { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 1025000 }, - { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(8), 1075000 }, - { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(9), 1075000 }, - { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(10), 1100000 }, - { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(11), 1100000 }, - { 1, { 972000, HFPLL, 1, 0, 0x24 }, L2(12), 1125000 }, - { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(13), 1125000 }, - { 1, { 1080000, HFPLL, 1, 0, 0x28 }, L2(14), 1175000 }, - { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1175000 }, - { 1, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1200000 }, - { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(17), 1200000 }, - { 1, { 1296000, HFPLL, 1, 0, 0x30 }, L2(18), 1225000 }, - { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(19), 1225000 }, - { 1, { 1404000, HFPLL, 1, 0, 0x34 }, L2(19), 1237500 }, - { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(20), 1237500 }, - { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(21), 1250000 }, - { 1, { 1674000, HFPLL, 1, 0, 0x3A }, L2(22), 1250000 }, - { 1, { 1728000, HFPLL, 1, 0, 0x3C }, L2(23), 1262500 }, - { 1, { 1809000, HFPLL, 1, 0, 0x3E }, L2(21), 1262500 }, - { 1, { 1890000, HFPLL, 1, 0, 0x40 }, L2(21), 1300000 }, - { 1, { 1998000, HFPLL, 1, 0, 0x42 }, L2(20), 1325000 }, - { 1, { 2106000, HFPLL, 1, 0, 0x44 }, L2(20), 1350000 }, - { 0, { 0 } } -}; - static struct acpu_level acpu_freq_tbl_8960_kraitv2_nom[] = { - { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 900000 }, - { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 900000 }, - { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(2), 925000 }, - { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(3), 925000 }, - { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(4), 950000 }, - { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(5), 950000 }, - { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 975000 }, - { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 975000 }, - { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(8), 1025000 }, - { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(9), 1025000 }, - { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(10), 1050000 }, - { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(11), 1050000 }, - { 1, { 972000, HFPLL, 1, 0, 0x24 }, L2(12), 1075000 }, - { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(13), 1075000 }, - { 1, { 1080000, HFPLL, 1, 0, 0x28 }, L2(14), 1125000 }, - { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1125000 }, - { 1, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1150000 }, - { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(17), 1150000 }, - { 1, { 1296000, HFPLL, 1, 0, 0x30 }, L2(18), 1175000 }, - { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(19), 1175000 }, - { 1, { 1404000, HFPLL, 1, 0, 0x34 }, L2(19), 1187500 }, - { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(20), 1187500 }, - { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(21), 1200000 }, - { 1, { 1674000, HFPLL, 1, 0, 0x3A }, L2(22), 1200000 }, - { 1, { 1728000, HFPLL, 1, 0, 0x3C }, L2(23), 1250000 }, - { 1, { 1809000, HFPLL, 1, 0, 0x3E }, L2(21), 1275000 }, - { 1, { 1900000, HFPLL, 1, 0, 0x40 }, L2(21), 1300000 }, - { 1, { 1998000, HFPLL, 1, 0, 0x42 }, L2(20), 1325000 }, - { 1, { 2106000, HFPLL, 1, 0, 0x44 }, L2(20), 1350000 }, - { 0, { 0 } } -}; - -static struct acpu_level acpu_freq_tbl_8960_kraitv2_fast[] = { - { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 850000 }, - { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 850000 }, - { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(2), 875000 }, - { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(3), 875000 }, - { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(4), 900000 }, - { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(5), 900000 }, - { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 925000 }, - { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 925000 }, - { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(8), 975000 }, - { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(9), 975000 }, - { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(10), 1000000 }, - { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(11), 1000000 }, - { 1, { 972000, HFPLL, 1, 0, 0x24 }, L2(12), 1025000 }, - { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(13), 1025000 }, - { 1, { 1080000, HFPLL, 1, 0, 0x28 }, L2(14), 1075000 }, - { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1075000 }, - { 1, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1100000 }, - { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(17), 1100000 }, - { 1, { 1296000, HFPLL, 1, 0, 0x30 }, L2(18), 1125000 }, - { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(19), 1125000 }, - { 1, { 1404000, HFPLL, 1, 0, 0x34 }, L2(19), 1137500 }, - { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(20), 1137500 }, - { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(21), 1150000 }, - { 1, { 1674000, HFPLL, 1, 0, 0x3A }, L2(22), 1175000 }, - { 1, { 1728000, HFPLL, 1, 0, 0x3C }, L2(23), 1200000 }, - { 1, { 1809000, HFPLL, 1, 0, 0x3E }, L2(21), 1250000 }, - { 1, { 1900000, HFPLL, 1, 0, 0x40 }, L2(21), 1300000 }, - { 1, { 1998000, HFPLL, 1, 0, 0x42 }, L2(20), 1325000 }, - { 1, { 2106000, HFPLL, 1, 0, 0x44 }, L2(20), 1350000 }, - { 0, { 0 } } -}; - -static struct acpu_level acpu_freq_tbl_8960_kraitv2_f3[] = { { 0, { STBY_KHZ, QSB, 0, 0, 0x00 }, L2(0), 850000 }, { 1, { 384000, PLL_8, 0, 2, 0x00 }, L2(1), 850000 }, - { 1, { 432000, HFPLL, 2, 0, 0x20 }, L2(2), 875000 }, - { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(3), 875000 }, - { 1, { 540000, HFPLL, 2, 0, 0x28 }, L2(4), 900000 }, - { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(5), 900000 }, - { 1, { 648000, HFPLL, 1, 0, 0x18 }, L2(6), 925000 }, - { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 925000 }, - { 1, { 756000, HFPLL, 1, 0, 0x1C }, L2(8), 975000 }, - { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(9), 975000 }, - { 1, { 864000, HFPLL, 1, 0, 0x20 }, L2(10), 1000000 }, - { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(11), 1000000 }, - { 1, { 972000, HFPLL, 1, 0, 0x24 }, L2(12), 1012500 }, - { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(13), 1012500 }, - { 1, { 1080000, HFPLL, 1, 0, 0x28 }, L2(14), 1050000 }, + { 0, { 432000, HFPLL, 2, 0, 0x20 }, L2(7), 850000 }, + { 1, { 486000, HFPLL, 2, 0, 0x24 }, L2(7), 850000 }, + { 0, { 540000, HFPLL, 2, 0, 0x28 }, L2(7), 850000 }, + { 1, { 594000, HFPLL, 1, 0, 0x16 }, L2(7), 850000 }, + { 0, { 648000, HFPLL, 1, 0, 0x18 }, L2(7), 900000 }, + { 1, { 702000, HFPLL, 1, 0, 0x1A }, L2(7), 900000 }, + { 0, { 756000, HFPLL, 1, 0, 0x1C }, L2(8), 950000 }, + { 1, { 810000, HFPLL, 1, 0, 0x1E }, L2(9), 950000 }, + { 0, { 864000, HFPLL, 1, 0, 0x20 }, L2(10), 975000 }, + { 1, { 918000, HFPLL, 1, 0, 0x22 }, L2(11), 975000 }, + { 0, { 972000, HFPLL, 1, 0, 0x24 }, L2(12), 1025000 }, + { 1, { 1026000, HFPLL, 1, 0, 0x26 }, L2(13), 1025000 }, + { 0, { 1080000, HFPLL, 1, 0, 0x28 }, L2(14), 1050000 }, { 1, { 1134000, HFPLL, 1, 0, 0x2A }, L2(15), 1050000 }, - { 1, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1075000 }, + { 0, { 1188000, HFPLL, 1, 0, 0x2C }, L2(16), 1075000 }, { 1, { 1242000, HFPLL, 1, 0, 0x2E }, L2(17), 1075000 }, - { 1, { 1296000, HFPLL, 1, 0, 0x30 }, L2(18), 1100000 }, - { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(19), 1100000 }, - { 1, { 1404000, HFPLL, 1, 0, 0x34 }, L2(19), 1112500 }, - { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(20), 1112500 }, - { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(21), 1125000 }, - { 1, { 1674000, HFPLL, 1, 0, 0x3A }, L2(22), 1175000 }, + { 0, { 1296000, HFPLL, 1, 0, 0x30 }, L2(18), 1125000 }, + { 1, { 1350000, HFPLL, 1, 0, 0x32 }, L2(19), 1125000 }, + { 0, { 1404000, HFPLL, 1, 0, 0x34 }, L2(19), 1125000 }, + { 1, { 1458000, HFPLL, 1, 0, 0x36 }, L2(20), 1150000 }, + { 1, { 1512000, HFPLL, 1, 0, 0x38 }, L2(21), 1150000 }, + { 1, { 1674000, HFPLL, 1, 0, 0x3A }, L2(22), 1200000 }, { 1, { 1728000, HFPLL, 1, 0, 0x3C }, L2(23), 1200000 }, - { 1, { 1809000, HFPLL, 1, 0, 0x3E }, L2(21), 1250000 }, - { 1, { 1900000, HFPLL, 1, 0, 0x40 }, L2(21), 1300000 }, - { 1, { 1998000, HFPLL, 1, 0, 0x42 }, L2(20), 1325000 }, - { 1, { 2106000, HFPLL, 1, 0, 0x44 }, L2(20), 1350000 }, + { 1, { 1809000, HFPLL, 1, 0, 0x3E }, L2(23), 1250000 }, + { 1, { 1900000, HFPLL, 1, 0, 0x40 }, L2(23), 1300000 }, { 0, { 0 } } }; @@ -1225,7 +1104,7 @@ static void __init hfpll_init(struct sca } /* Voltage regulator initialization. */ -static void regulator_init(int set_vdd) +static void __init regulator_init(int set_vdd) { int cpu, ret; struct scalable *sc; @@ -1256,7 +1135,7 @@ static void regulator_init(int set_vdd) } /* Set initial rate for a given core. */ -static void init_clock_sources(struct scalable *sc, +static void __init init_clock_sources(struct scalable *sc, struct core_speed *tgt_s) { uint32_t regval; @@ -1286,7 +1165,7 @@ static void init_clock_sources(struct sc sc->first_set_call = true; } -static void per_cpu_init(void *data) +static void __init per_cpu_init(void *data) { struct acpu_level *max_acpu_level = data; int cpu = smp_processor_id(); @@ -1314,7 +1193,7 @@ static void __init bus_init(unsigned int #ifdef CONFIG_CPU_FREQ_MSM static struct cpufreq_frequency_table freq_table[NR_CPUS][FREQ_TABLE_SIZE]; -static void cpufreq_table_init(void) +static void __init cpufreq_table_init(void) { int cpu; @@ -1398,7 +1277,6 @@ static struct notifier_block __cpuinitda .notifier_call = acpuclock_cpu_callback, }; -#if 0 static const int krait_needs_vmin(void) { switch (read_cpuid_id()) { @@ -1413,11 +1291,14 @@ static const int krait_needs_vmin(void) static void kraitv2_apply_vmin(struct acpu_level *tbl) { - for (; tbl->speed.khz != 0; tbl++) - if (tbl->vdd_core < MIN_VDD_SC) - tbl->vdd_core = MIN_VDD_SC; + for (; tbl->speed.khz != 0; tbl++) { + tbl->vdd_core_save = tbl->vdd_core; + if (tbl->vdd_core < VMIN) { + pr_info("%8u: cur-vdd %4d - new-vdd %4d", tbl->speed.khz, tbl->vdd_core, VMIN); + tbl->vdd_core = VMIN; + } + } } -#endif #ifdef CONFIG_SEC_L1_DCACHE_PANIC_CHK uint32_t global_sec_pvs_value; @@ -1516,15 +1397,18 @@ static struct acpu_level * __init select } else { BUG(); } -#if 0 if (krait_needs_vmin()) kraitv2_apply_vmin(acpu_freq_tbl); -#endif /* Find the max supported scaling frequency. */ - for (l = acpu_freq_tbl; l->speed.khz != 0; l++) - if (l->use_for_scaling) - max_acpu_level = l; + for (l = acpu_freq_tbl; l->speed.khz != 0; l++) { + if (l->use_for_scaling) { + if (l->speed.khz <= MAX_FREQ_LIMIT) + max_acpu_level = l; + else + l->use_for_scaling = 0; + } + } BUG_ON(!max_acpu_level); pr_info("Max ACPU freq: %u KHz\n", max_acpu_level->speed.khz); @@ -1590,4 +1474,18 @@ void acpuclk_set_vdd(unsigned int khz, i } mutex_unlock(&driver_lock); } + +void acpuclk_set_vmin(int newvmin) +{ + int i; + + if (krait_needs_vmin()) { + if (newvmin >= MIN_VDD_SC && newvmin <= MAX_VDD_SC) { + VMIN = newvmin; + for (i = 0; acpu_freq_tbl[i].speed.khz; i++) + acpu_freq_tbl[i].vdd_core = acpu_freq_tbl[i].vdd_core_save; + kraitv2_apply_vmin(acpu_freq_tbl); + } + } +} #endif