Samsung VZW MB1 update
/drivers/video/msm/mdp4_util.c
blob:6b386a68ccb1f60ed66a58bdcf07f0102d18ccf9 -> blob:8caef01026d58bd22f43ebf3a8f6a1c4977b58f7
--- drivers/video/msm/mdp4_util.c
+++ drivers/video/msm/mdp4_util.c
@@ -35,6 +35,9 @@
struct mdp4_statistic mdp4_stat;
+#define MDP4_SW_RESET;
+
+
unsigned is_mdp4_hw_reset(void)
{
unsigned hw_reset = 0;
@@ -265,7 +268,7 @@ void mdp4_hw_init(void)
mdp_bus_scale_update_request(5);
-#ifdef MDP4_ERROR
+#ifdef MDP4_SW_RESET
/*
* Issue software reset on DMA_P will casue DMA_P dma engine stall
* on LCDC mode. However DMA_P does not stall at MDDI mode.
@@ -441,7 +444,7 @@ irqreturn_t mdp4_isr(int irq, void *ptr)
mdp4_dmap_done_dsi_cmd(0);
#else
else { /* MDDI */
- mdp4_dma_p_done_mddi(dma);
+ mdp4_dmap_done_mddi(0);
mdp_pipe_ctrl(MDP_DMA2_BLOCK,
MDP_BLOCK_POWER_OFF, TRUE);
complete(&dma->comp);
@@ -492,7 +495,7 @@ irqreturn_t mdp4_isr(int irq, void *ptr)
mdp4_overlay0_done_dsi_cmd(0);
#else
if (panel & MDP4_PANEL_MDDI)
- mdp4_overlay0_done_mddi(dma);
+ mdp4_overlay0_done_mddi(0);
#endif
}
mdp_hw_cursor_done();
@@ -3878,6 +3881,107 @@ error:
return ret;
}
+#define QSEED_TABLE_1_COUNT 2
+#define QSEED_TABLE_2_COUNT 1024
+
+static uint32_t mdp4_pp_block2qseed(uint32_t block)
+{
+ uint32_t valid = 0;
+ switch (block) {
+ case MDP_BLOCK_VG_1:
+ case MDP_BLOCK_VG_2:
+ valid = 0x1;
+ break;
+ default:
+ break;
+ }
+ return valid;
+}
+
+static int mdp4_qseed_access_cfg(struct mdp_qseed_cfg_data *cfg)
+{
+ int i, ret = 0;
+ uint32_t base = (uint32_t) (MDP_BASE + mdp_block2base(cfg->block));
+ uint32_t *values;
+
+ if ((cfg->table_num != 1) && (cfg->table_num != 2)) {
+ ret = -ENOTTY;
+ goto error;
+ }
+
+ if (((cfg->table_num == 1) && (cfg->len != QSEED_TABLE_1_COUNT)) ||
+ ((cfg->table_num == 2) && (cfg->len != QSEED_TABLE_2_COUNT))) {
+ ret = -EINVAL;
+ goto error;
+ }
+
+ values = kmalloc(cfg->len * sizeof(uint32_t), GFP_KERNEL);
+ if (!values) {
+ ret = -ENOMEM;
+ goto error;
+ }
+
+ base += (cfg->table_num == 1) ? MDP4_QSEED_TABLE1_OFF :
+ MDP4_QSEED_TABLE2_OFF;
+
+ if (cfg->ops & MDP_PP_OPS_WRITE) {
+ ret = copy_from_user(values, cfg->data,
+ sizeof(uint32_t) * cfg->len);
+ if (ret) {
+ pr_warn("%s: Error copying from user, %d", __func__,
+ ret);
+ ret = -EINVAL;
+ goto err_mem;
+ }
+ for (i = 0; i < cfg->len; i++) {
+ if (!(base & 0x3FF))
+ wmb();
+ MDP_OUTP(base , values[i]);
+ base += sizeof(uint32_t);
+ }
+ } else if (cfg->ops & MDP_PP_OPS_READ) {
+ for (i = 0; i < cfg->len; i++) {
+ values[i] = inpdw(base);
+ if (!(base & 0x3FF))
+ rmb();
+ base += sizeof(uint32_t);
+ }
+ ret = copy_to_user(cfg->data, values,
+ sizeof(uint32_t) * cfg->len);
+ if (ret) {
+ pr_warn("%s: Error copying to user, %d", __func__, ret);
+ ret = -EINVAL;
+ goto err_mem;
+ }
+ }
+
+err_mem:
+ kfree(values);
+error:
+ return ret;
+}
+
+int mdp4_qseed_cfg(struct mdp_qseed_cfg_data *cfg)
+{
+ int ret = 0;
+
+ if (!mdp4_pp_block2qseed(cfg->block)) {
+ ret = -ENOTTY;
+ goto error;
+ }
+
+ if ((cfg->ops & MDP_PP_OPS_READ) && (cfg->ops & MDP_PP_OPS_WRITE)) {
+ ret = -EPERM;
+ pr_warn("%s: Cannot read and write on the same request\n",
+ __func__);
+ goto error;
+ }
+
+ ret = mdp4_qseed_access_cfg(cfg);
+
+error:
+ return ret;
+}
u32 mdp4_get_mixer_num(u32 panel_type)
{
u32 mixer_num;